Low-temperature operation of silicon dynamic random-access memoriesWYNS, P; ANDERSON, R. L.I.E.E.E. transactions on electron devices. 1989, Vol 36, Num 8, pp 1423-1428, issn 0018-9383, 6 p.Article

Dual-ported memorySCAYSBROOK, F. F.Review of scientific instruments. 1986, Vol 57, Num 1, pp 122-123, issn 0034-6748Article

Interfacing multi-processors using devices with dual-port RAMGONZALES, D. R.Microelectronics. 1985, Vol 16, Num 3, pp 5-12, issn 0026-2692Article

All points addressable raster display memoryMATICK, R; LING, D. T; GUPTA, S et al.IBM journal of research and development. 1984, Vol 28, Num 4, pp 379-392, issn 0018-8646Article

THE EFFECT OF PARASITIC CAPACITANCES ON THE CIRCUIT SPEED OF GAAS MESFET RING OSCILLATORSCHANG CTM; NAMORDI MR; WHITE WA et al.1982; IEEE TRANSACTIONS ON ELECTRON DEVICES; ISSN 0018-9383; USA; DA. 1982; VOL. 29; NO 11; PP. 1805-1809; BIBL. 8 REF.Article

A 32K ASIC synchronous RAM using a two-transistor basic cellYUEN, A; TSAO, P; YIN, P et al.IEEE journal of solid-state circuits. 1989, Vol 24, Num 1, pp 57-61, issn 0018-9200, 5 p.Article

A REVIEW OF RAM TESTING METHODOLOGICSCORSI A; MORANDI C.1983; MICROELECTRONICS; ISSN 0026-2692; GBR; DA. 1983; VOL. 14; NO 2; PP. 55-71; BIBL. 29 REF.Article

MINIATURIZATION DEGREE OF DYNAMIC MOS RAM CELLS WITH READOUT SIGNAL GAINTSUCHIYA T; NAKAJIMA S.1982; IEEE TRANSACTIONS ON ELECTRON DEVICES; ISSN 0018-9383; USA; DA. 1982; VOL. 29; NO 11; PP. 1713-1717; BIBL. 6 REF.Article

Optoelectronic dynamic random access memory cell utilizing a three-terminal N-channel self-aligned double-heterostructure optoelectronic switchTAYLOR, G. W; CRAWFORD, D. L; SIMMONS, J. G et al.Applied physics letters. 1989, Vol 54, Num 6, pp 543-545, issn 0003-6951, 3 p.Article

A 12-ns ECL I/O 256K×1-bit SRAM using a 1-υm BiCMOS technologyKERTIS, R. A; SMITH, D. D; BOWMAN, T. L et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1048-1053, issn 0018-9200Article

Dual-operating-voltage scheme for a single 5-V 16-Mbit DRAMHORIGUCHI, M; AOKI, M; TANAKA, H et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1128-1132, issn 0018-9200Article

Soft error rates in 64 K and 256 K DRAMsHAQUE, A. K. M. M; YATES, J; STEVENS, D et al.Electronics Letters. 1986, Vol 22, Num 22, pp 1188-1189, issn 0013-5194Article

A 256K-bit dynamic RAM with high alpha immunityENDO, A; ITO, S; ISHIHARA, M et al.Microelectronics. 1984, Vol 15, Num 5, pp 5-15, issn 0026-2692Article

An effect of the subthreshold current on scaled-down MOS dynamic RAM'sMASHIKO, K; YAMADA, M; NAGAYAMA, Y et al.IEEE journal of solid-state circuits. 1983, Vol 18, Num 4, pp 429-431, issn 0018-9200Article

Beam-induced seeded lateral epitaxy with suppressed impurity diffusion for a three-dimensional DRAM cell fabricationOHKURA, M; KUSUKAWA, K; SUNAMI, H et al.I.E.E.E. transactions on electron devices. 1989, Vol 36, Num 2, pp 333-339, issn 0018-9383, 7 p.Article

A 4-ns 4K×1-bit two-port BiCMOS SRAMTSEN-SHAU YANG; HOROWITZ, M. A; WOOLEY, B. A et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1030-1040, issn 0018-9200Article

An 11-ns 8K×18 CMOS static RAM with 0.5-μm devicesWONG, D. T; ADAMS, R. D; ARUP BHATTACHARYYA et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1095-1103, issn 0018-9200Article

Smart dual-port RAM: HD63310HAYASHI, S; ABE, M.Hitachi review. 1986, Vol 35, Num 5, pp 247-250, issn 0018-277XArticle

Hot electron improvement in MOS RAM's based on epitaxial substrateSATOH, S; EIMORI, T; MATSUMOTO, H et al.Japanese journal of applied physics. 1985, Vol 24, Num 3, pp 184-186, issn 0021-4922Article

Upper bounds for sorting integers on random access machinesKIRKPATRICK, D; REISCH, S.Theoretical computer science. 1984, Vol 28, Num 3, pp 263-276, issn 0304-3975Article

A 14-ns 1-Mbit CMOS SRAM with variable bit organizationKOHNO, Y; WADA, T; ANAMI, K et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1060-1066, issn 0018-9200Article

A 25-ns low-power full-CMOS 1-Mbit (128K×8) SRAMCHU, S. T; DIKKEN, J; HARTGRING, C. D et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1078-1084, issn 0018-9200Article

Charle losses of N-doped trench cellsRISCH, L; MALY, R; BERGNER, W et al.Japanese journal of applied physics. 1988, Vol 27, Num 11, pp L2223-L2226, issn 0021-4922, part 2Article

Contribution à l'étude du test aléatoire de mémoires RAM = Study of the random test of RAM memoryFUENTES, Antoine; DAVID, René.1986, 110 pThesis

LSI memoriesNOGUCHI, E; TOYODA, K; FUKUSHIMA, T et al.Fujitsu scientific and technical journal. 1985, Vol 21, Num 3, pp 337-369, issn 0016-2523Article