Reconfigurable technology : FPGAs and reconfigurable processors for computing and communications III (Denver CO, 21-22 August 2001)Schewel, John; Athanas, Peter M; James-Roxby, Philip B et al.SPIE proceedings series. 2001, isbn 0-8194-4249-6, V, 174 p, isbn 0-8194-4249-6Conference Proceedings

Model-based performance analysis for reconfigurable coprocessorsCHARLWOOD, Stephen M; MANGNALL, Jonathan P; QUIGLEY, Steven F et al.SPIE proceedings series. 2001, pp 36-47, isbn 0-8194-4249-6Conference Paper

Reconfigurable processors for handhelds and wearables: Application analysisENZLER, Rolf; PLATZNER, Marco; PLESSL, Christian et al.SPIE proceedings series. 2001, pp 135-146, isbn 0-8194-4249-6Conference Paper

Reconfiguring an FPGA-based RISC for LNS arithmeticARNOLD, Mark G; WINKEL, Mark D.SPIE proceedings series. 2001, pp 88-98, isbn 0-8194-4249-6Conference Paper

Programming High Performance reconfigurable ComputersSMITH, Melissa C; PETERSON, Gregory D.SPIE proceedings series. 2001, pp 60-68, isbn 0-8194-4249-6Conference Paper

Digital FPGA implementation for Bellman-Ford computationFUNG, Wai-Ming; NG, Hoi-Shing; LAM, Kai-Pui et al.SPIE proceedings series. 2001, pp 76-87, isbn 0-8194-4249-6Conference Paper

Spatially reconfigurable module for FIR filtersPLAKS, Toomas P.SPIE proceedings series. 2001, pp 107-115, isbn 0-8194-4249-6Conference Paper

Configuration subsystem design exploration for domain-specific reconfigurable technologiesVASILKO, Milan.SPIE proceedings series. 2001, pp 48-59, isbn 0-8194-4249-6Conference Paper

A real-time debugger with bitstream configurator & 'C' language design control for FPGAsCASSELMAN, Steve; SCHEWEL, John; WARTEL, Frank et al.SPIE proceedings series. 2001, pp 69-75, isbn 0-8194-4249-6Conference Paper

A run-time reconfigurable 2D Discrete Wavelet Transform using JBitsBALLAGH, Jonathan; ATHANAS, Peter; KELLER, Eric et al.SPIE proceedings series. 2001, pp 116-124, isbn 0-8194-4249-6Conference Paper

Highly reconfigurable communication protocol multiplexing element for SCOPHBREBNER, Gordon.SPIE proceedings series. 2001, pp 99-106, isbn 0-8194-4249-6Conference Paper

Temporal partitioning of circuits for advanced partially reconfigurable systemsMOHAN, R; DASU, A; PANCHANATHAN, S et al.SPIE proceedings series. 2001, pp 27-35, isbn 0-8194-4249-6Conference Paper

Transformation from C-program to circuitry for a dynamically reconfigurable cell array processorMORIHSITA, Takayuki; KOMOKU, Kiyotaka; HATANO, Fumihiro et al.SPIE proceedings series. 2001, pp 10-17, isbn 0-8194-4249-6Conference Paper

Signal processing for multiuser wireless systems on reconfigurable platformsTHOMAS, Joseph.SPIE proceedings series. 2001, pp 161-172, isbn 0-8194-4249-6Conference Paper

A network processor architecture for flexible buffer management in very high-speed line interfacesSHIMONISHI, Hideyuki; MURASE, Tutomu.SPIE proceedings series. 2001, pp 125-134, isbn 0-8194-4249-6Conference Paper

XHWIF: A portable hardware interface for reconfigurable computingSUNDARARAJAN, Prasanna; GUCCIONE, Steven A; LEVI, Delon et al.SPIE proceedings series. 2001, pp 155-160, isbn 0-8194-4249-6Conference Paper

Fault injection emulator for Field Programmable Gate ArraysSLAUGHTER, Thomas; STROUD, Charles; EMMERT, John et al.SPIE proceedings series. 2001, pp 1-9, isbn 0-8194-4249-6Conference Paper

Designing application -specific cores using JBits: A run-time parameterizable FIR filterJAMES-ROXBY, Philip.SPIE proceedings series. 2001, pp 18-26, isbn 0-8194-4249-6Conference Paper

Variable Length Decoder on Dynamically Reconfigurable Cell Array ProcessorKOMOKU, Kiyotaka; MORISHITA, Takayuki; HATANO, Fumihiro et al.SPIE proceedings series. 2001, pp 147-154, isbn 0-8194-4249-6Conference Paper