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Analysis of the effects of time delay in clock recovery circuits based on phase-locked loodsZIBAR, Darko; OXENLØWE, Leif K; CLAUSEN, Anders T et al.Lasers and Electro-optics Society. 2004, isbn 0-7803-8557-8, 2Vol, Vol1, 316-317Conference Paper

Optical Clock RecoveryCHEN, Z; SUN, H; MA, S et al.Proceedings of SPIE, the International Society for Optical Engineering. 2009, Vol 7234, issn 0277-786X, isbn 978-0-8194-7480-3 0-8194-7480-0, 1Vol, 72340H.1-72340H.8Conference Paper

Fast timing recovery for linearly and non-linearly modulated systemsKAI SHI; SERPEDIN, Erchin.Asilomar Conference on Signals, Systems & Computers. 2004, isbn 0-7803-8622-1, 2Vol, vol 1, 1015-1019Conference Paper

Simultaneous clock recovery for 160 Gbit/s optical time-division multiplexing signal using phase modulationZHANG, S. J; LIU, Y; GOMEZ-AGIS, F et al.Electronics letters. 2011, Vol 47, Num 22, pp 1238-1240, issn 0013-5194, 3 p.Article

An interpolation filter based on spline functions for non-synchronized timing recoveryHAFTBARADARAN, Afshin; MARTIN, Ken.IEEE International Symposium on Circuits and Systems. 2004, pp 309-312, isbn 0-7803-8251-X, 4 p.Conference Paper

A Novel Clock Recovery Scheme for ATSC ReceiversJINGSONG XIA.IEEE transactions on broadcasting. 2008, Vol 54, Num 2, pp 276-282, issn 0018-9316, 7 p.Article

Self-clocked 80 Gbits/s optical time-domain multiplexing transmission with clock distribution based on amplitude discriminationKRAVTSOV, Konstantin; PRUCNAL, Paul R.Optics letters. 2009, Vol 34, Num 7, pp 944-946, issn 0146-9592, 3 p.Article

Low latency synchronization through speculationKINNIMENT, D. J; YAKOVLEV, A. V.Lecture notes in computer science. 2004, pp 278-288, issn 0302-9743, isbn 3-540-23095-5, 11 p.Conference Paper

Single reference continuous rate clock and data recovery from 30MBit/s to 3.2GBit/sFRAMBACH, Jan-Peter; HEIJNA, Roeland; KRÖSSCHELL, Rob et al.Custom integrated circuits conference. 2002, pp 375-378, isbn 0-7803-7250-6, 4 p.Conference Paper

Low-jitter design method based on ωn-domain jitter analysis for 10 Gbit/s clock and data recovery ICsKISHINE, K; INABA, H; NAKAMURA, Ma et al.Electronics letters. 2009, Vol 45, Num 16, pp 808-809, issn 0013-5194, 2 p.Article

Symbol-Rate Clock Recovery for Integrating DFE ReceiversTAKEYA, Tsutomu; KURODA, Tadahiro.IEICE transactions on fundamentals of electronics, communications and computer science. 2013, Vol 96, Num 3, pp 705-712, issn 0916-8508, 8 p.Article

Carrier-Phase-Based Two-Way Satellite Time and Frequency TransferFUJIEDA, Miho; GOTOH, Tadahiro; NAKAGAWA, Fumimaru et al.IEEE transactions on ultrasonics, ferroelectrics, and frequency control. 2012, Vol 59, Num 12, pp 2625-2630, issn 0885-3010, 6 p.Article

Skew tolerant digital CDR architecture for LVDS video transceiver applicationsSARMENTO, J. A.Electronics letters. 2010, Vol 46, Num 8, pp 578-580, issn 0013-5194, 3 p.Article

Analysis of Multiwavelength Clock Recovery based on Stimulated Brillouin ScatteringMING CHEN; SUCHUN FENG; SHUISHENG JIAN et al.Proceedings of SPIE, the International Society for Optical Engineering. 2009, Vol 7514, issn 0277-786X, isbn 978-0-8194-7903-7 0-8194-7903-9, 1Vol, 75140B.1-75140B.6Conference Paper

All-optical clock recovery CSRZ-format data at 40Gbit/s using SOA-based ring laserZHIXIN CHEN.Proceedings of SPIE, the International Society for Optical Engineering. 2008, Vol 7134, issn 0277-786X, isbn 978-0-8194-7374-5 0-8194-7374-X, 71343G.1-71343G.8, 2Conference Paper

Investigation of multiwavelength clock recovery based on heterodyne beats of sideband-filtered signalVON LERBER, T; TUOMINEN, J; LUDVIGSEN, H et al.Optics communications. 2007, Vol 271, Num 1, pp 87-90, issn 0030-4018, 4 p.Article

Noncoherent data transition tracking loops for symbol synchronization in digital communication receiversSIMON, Marvin K; TKACENKO, Andre.IEEE transactions on communications. 2006, Vol 54, Num 5, pp 889-899, issn 0090-6778, 11 p.Article

Extended gardner detector for improved symbol-timing recovery of M-PSK signalsGAPPMAIR, Wilfried; CIONI, Stefano; CORAZZA, Giovanni E et al.IEEE transactions on communications. 2006, Vol 54, Num 11, pp 1923-1927, issn 0090-6778, 5 p.Article

Acquisition-time estimation for over 10Gbit/s clock and data recovery ICsKISHINE, K; ONODERA, H.Electronics Letters. 2005, Vol 41, Num 23, pp 1273-1275, issn 0013-5194, 3 p.Article

A novel timing recovery for read Channel systems using a feedback cross position control methodKAWABE, Akira; OKAMOTO, Koji; YAMAMOTO, Takashi et al.SPIE proceedings series. 2004, pp 262-271, isbn 0-8194-5293-9, 10 p.Conference Paper

A novel half-rate architecture for high-speed clock and data recoveryQIURONG HE; FENG, Milton.IEEE Systems-on-chip conference. 2004, pp 351-354, isbn 0-7803-8445-8, 1Vol, 4 p.Conference Paper

Performance analysis and simplification of Digital Zero Phase Start (DZPS) employed in data storage timing recovery systemsJIN XIE; VIJAVA KUMAR, B. V. K.IEEE Global Telecommunications Conference. 2004, pp 1118-1122, isbn 0-7803-8794-5, 5 p.Conference Paper

A 1/8-rate clock and data recovery architecture for high-speed communication systemsSAMENI, Pedram; MIRABBASI, Shahriar.IEEE International Symposium on Circuits and Systems. 2004, pp 305-308, isbn 0-7803-8251-X, 4 p.Conference Paper

A 128Mb multi port media DRAM with four independent 4Gb/s serial portsLEE, Seunghoon; KWON, Kee-Won; KIM, Changhyun et al.Symposium on VLSI Circuits. 2003, pp 34-35, isbn 0-7803-8287-0, 1Vol, 2 p.Conference Paper

A 25-Gb/s 5-mW CMOS CDR/DeserializerJUNG, Jun Won; RAZAVI, Behzad.IEEE journal of solid-state circuits. 2013, Vol 48, Num 3, pp 684-697, issn 0018-9200, 14 p.Article

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