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Careful examination on the asymmetric Vfb shift problem for poly-Si/HfSiON gate stack and its solution by the Hf concentration control in the dielectric near the poly-Si interface with small EOT expenseKOYAMA, Masato; KAMIMUTA, Yuuichi; INO, Tsunehiro et al.International Electron Devices Meeting. 2004, pp 499-502, isbn 0-7803-8684-1, 1Vol, 4 p.Conference Paper

Structure of the breakdown spot during progressive breakdown of ultra-thin gate oxidesPALUMBO, F; LOMBARDO, S; PEY, K. L et al.IEEE international reliability physics symposium. 2004, pp 583-584, isbn 0-7803-8315-X, 1Vol, 2 p.Conference Paper

Modeling and characterization of gate oxide reliabilityLEE, J. C; IH-CHIN CHEN; CHENMING HU et al.I.E.E.E. transactions on electron devices. 1988, Vol 35, Num 12, pp 2268-2278, issn 0018-9383Article

A novel gate-suppression technique for ESD protectionMENG MIAO; SHURONG DONG; MINGLIANG LI et al.Microelectronics and reliability. 2012, Vol 52, Num 8, pp 1598-1601, issn 0026-2714, 4 p.Conference Paper

Subnanometer-precision metrology for 100nm gate linewidth controlMONAHAN, K. M; MACNAUGHTON, C; NG, W et al.SPIE proceedings series. 1998, pp 110-123, isbn 0-8194-2777-2Conference Paper

Gate technology for 89 GHz vertical doping engineered Si metal-oxide semiconductor field effect transistorJEON, D. Y; TENNANT, D. M; KIM, Y. O et al.Journal of vacuum science & technology. B. Microelectronics and nanometer structures. Processing, measurement and phenomena. 1992, Vol 10, Num 6, pp 2922-2926, issn 1071-1023Conference Paper

Platinum-platinum oxide gate pH ISFETTSUKADA, K; MIYAHARA, Y; MIYAGI, H et al.Japanese journal of applied physics. 1989, Vol 28, Num 12, pp 2450-2453, issn 0021-4922, 1Article

Evaluation of phase-edge phase-shifting mask for sub-0.18 μm gate patterns in logic devicesCHA, D.-H; KYE, J.-W; SEONG, N.-G et al.SPIE proceedings series. 1998, pp 46-54, isbn 0-8194-2779-9Conference Paper

Advanced gate stack, source/drain and channel engineering for Si-based CMOS : naw materials, processes, and equipment (Quebec PQ, 16-18 May 2005)Gusev, Evgeni P; Iwai, Hiroshi; Öztürk, Mehmet C et al.Proceedings - Electrochemical Society. 2005, issn 0161-6374, isbn 1-56677-463-2, XV, 634 p, isbn 1-56677-463-2Conference Proceedings

Line edge roughness: Characterization, modeling and impact on device behaviorCROON, J. A; STORMS, G; WINKELMEIER, S et al.IEDm : international electron devices meeting. 2002, pp 307-310, isbn 0-7803-7462-2, 4 p.Conference Paper

Effect of n+―polycrystalline silicon gate rapid thermal annealing on the electrical properties of the gate oxideKOREC, J; STEFFEN, A; MCGINTY, G. K et al.Thin solid films. 1988, Vol 162, pp 21-28, issn 0040-6090Article

Symmetrical 45nm PMOS on (110) substrate with excellent S/D extension distribution and mobility enhancementHWANG, J. R; HO, J. H; LIN, H. S et al.Symposium on VLSI Technology. sd, pp 90-91, isbn 0-7803-8289-7, 1Vol, 2 p.Conference Paper

Gate dielectric breakdown : A focus on ESD protectionWEIR, Bonnie E; LEUNG, Che-Choi; SILVERMAN, Paul J et al.IEEE international reliability physics symposium. 2004, pp 399-404, isbn 0-7803-8315-X, 1Vol, 6 p.Conference Paper

0.18 μm optical lithography performances using an alternating DUV phase shift maskTROUILLER, Y; BUFFET, N; MOURIER, T et al.SPIE proceedings series. 1998, pp 25-35, isbn 0-8194-2779-9Conference Paper

A novel method to characterize MOS transistors with mixed gate dielectric technologiesSIERGIEJ, R. R; WHITE, M. H.I.E.E.E. transactions on electron devices. 1992, Vol 39, Num 3, pp 734-737, issn 0018-9383Article

Correlation Between the Vth Adjustment of nMOSFETs With HfSiO Gate Oxide and the Energy Profile of the Bulk Trap DensitySAHHAF, S; DEGRAEVE, R; SRIVIDYA, V et al.IEEE electron device letters. 2010, Vol 31, Num 4, pp 272-274, issn 0741-3106, 3 p.Article

Multistep fault-collapsing method for spectral signature detecting in combinational networksTONG WU; YAO-SHENG ZHANG.International journal of electronics. 1990, Vol 68, Num 5, pp 647-655, issn 0020-7217Article

Operation of Graphene Transistors at Gigahertz FrequenciesLIN, Yu-Ming; JENKINS, Keith A; VALDES-GARCIA, Alberto et al.Nano letters (Print). 2009, Vol 9, Num 1, pp 422-426, issn 1530-6984, 5 p.Article

On the gate capacitance of mos structures in N-channel inversion layers on ternary chalcopyrite semiconductorsGHATAK, K. P; CHATTOPADHYAY, N; MONDAL, M et al.Applied physics. A, Solids and surfaces. 1989, Vol 48, Num 4, pp 365-371, issn 0721-7250Article

Surface mobility in N+ and P+ doped polysilicon gate PMOS transistorsAMM, D. T; MINGAM, H; DELPECH, P et al.I.E.E.E. transactions on electron devices. 1989, Vol 36, Num 5, pp 963-968, issn 0018-9383, 6 p.Article

The influence of substrate compensation on inter-electrode leakage and back-gating in GaAs MESFETGEORGE, P; KO, P. K; CHENMING HU et al.Solid-state electronics. 1991, Vol 34, Num 3, pp 233-252, issn 0038-1101, 20 p.Article

Ultra-submicrometer-gate AlGaAs/GaAs HEMT'sHAN, J; FERRY, D. K; NEWMAN, P et al.IEEE electron device letters. 1990, Vol 11, Num 5, pp 209-211, issn 0741-3106, 3 p.Article

Effective work function of NiSi/HfO2 gate stacks measured with X-ray photoelectron spectroscopyLEBEDINSKII, Yu. Yu; ZENKEVICH, A. V.Microelectronics and reliability. 2007, Vol 47, Num 4-5, pp 649-652, issn 0026-2714, 4 p.Conference Paper

Study of stress evolution during full silicidation for gate stacksTORREGIANI, C; KITTI, J. A; CAPPON, S et al.Proceedings - Electrochemical Society. 2005, pp 249-256, issn 0161-6374, isbn 1-56677-463-2, 8 p.Conference Paper

New concept of high-k integration in MOSFET's by a deposition through contact holesHARRISON, S; CORONEL, P; WACQUANT, F et al.Microelectronic engineering. 2004, Vol 72, Num 1-4, pp 321-325, issn 0167-9317, 5 p.Conference Paper

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