A state-constrained model for cellular nonlinear network optimizationCHOU, E. Y; SHEU, B. J; TSAI, R. H et al.IEEE transactions on circuits and systems. 1, Fundamental theory and applications. 1997, Vol 44, Num 5, pp 445-449, issn 1057-7122Article

Analog floating-gate synapses for general-purpose VLSI neural computationLEE, B. W; SHEU, B. J; HAN YANG et al.IEEE transactions on circuits and systems. 1991, Vol 38, Num 6, pp 654-658, issn 0098-4094, 5 p.Article

Modified Hopfield neural networks for retrieving the optimal solutionLEE, B. W; SHEU, B. J.IEEE transactions on neural networks. 1991, Vol 2, Num 1, pp 137-142, issn 1045-9227Article

Flexible architecture approach to knowledge-based analogue IC designSHEU, B. J; LEE, J. C; FUNG, A. H et al.IEE proceedings. Part G. Electronic circuits and systems. 1990, Vol 137, Num 4, pp 266-274, issn 0143-7089Article

Short-channel effects on MOS transistor capacitancesSHEU, B. J; KO, P. K.IEEE transactions on circuits and systems. 1986, Vol 33, Num 10, pp 1030-1032, issn 0098-4094Article

A simple method to determine channel widths for conventional and LDD MOSFET'sSHEU, B. J; KO, P. K.IEEE electron device letters. 1984, Vol 5, Num 11, pp 485-486, issn 0741-3106Article

VLSI design of optimization and image processing cellular neural networksCHOU, E. Y; SHEU, B. J; CHANG, R. C et al.IEEE transactions on circuits and systems. 1, Fundamental theory and applications. 1997, Vol 44, Num 1, pp 12-20, issn 1057-7122Article

A hardware annealing method for optimal solutions on cellular neural networksBANG, S. H; SHEU, B. J; CHOU, E. Y et al.IEEE transactions on circuits and systems. 2, Analog and digital signal processing. 1996, Vol 43, Num 6, pp 409-421, issn 1057-7130Article

Design and characterization of analog VLSI neural network modulesGOWDA, S. M; SHEU, B. J; CHOI, J et al.IEEE journal of solid-state circuits. 1993, Vol 28, Num 3, pp 301-313, issn 0018-9200Conference Paper

Self-reconstructing technique for expert system-based analog IC designsFUNG, A. H; LEE, B. W; SHEU, B. J et al.IEEE transactions on circuits and systems. 1989, Vol 36, Num 2, pp 318-321, issn 0098-4094, 4 p.Article

A knowledge-based approach to analog IC designSHEU, B. J; FUNG, A. H; YING-NAN LAI et al.IEEE transactions on circuits and systems. 1988, Vol 35, Num 2, pp 256-258, issn 0098-4094Article

Modeling charge injection in MOS analog switchesSHEU, B. J; SHIEH, J.-H; PATIL, M et al.IEEE transactions on circuits and systems. 1987, Vol 34, Num 2, pp 214-216, issn 0098-4094Article

Inverse-geometry dependence of MOS transistor electrical parametersHSU, M. C; SHEU, B. J.IEEE transactions on computer-aided design of integrated circuits and systems. 1987, Vol 6, Num 4, pp 582-585, issn 0278-0070Article

Source-and-drain series resistance of LDD MOSFET'sSHEU, B. J; HU, C; KO, P. K et al.IEEE electron device letters. 1984, Vol 5, Num 9, pp 365-367, issn 0741-3106Article

Compact VLSI neural network circuit with high-capacity dynamic synapsesPARK, Yoondong; LIAW, J.-S; SHEU, B. J et al.IEEE-INNS-ENNS international joint conference on neural networks. 2000, pp Vol4.214-218, isbn 0-7695-0619-4, 6VolConference Paper

Advances in efficient optical links to enhance desktop multimedia processor systemsTSAI, R. H; SHEU, B. J; KOSTRZEWSKI, A et al.IEEE transactions on circuits and systems for video technology. 1997, Vol 7, Num 4, pp 707-713, issn 1051-8215Article

Paralleled hardware annealing in multilevel Hopfield neural networks for optimal solutionsSA HYUN BANG; CHEN, O. T.-C; CHANG, J. C.-F et al.IEEE transactions on circuits and systems. 2, Analog and digital signal processing. 1995, Vol 42, Num 1, pp 46-49, issn 1057-7130Article

An adaptive vector quantizer based on the gold-washing method for image compressionCHEN, O. T.-C; SHEU, B. J; ZHEN ZHANG et al.IEEE transactions on circuits and systems for video technology. 1994, Vol 4, Num 2, pp 143-157, issn 1051-8215Article

A programmable analog VLSI neural network processor for communication receiversJOONGHO CHOI; SA HYUN BANG; SHEU, B. J et al.IEEE transactions on neural networks. 1993, Vol 4, Num 3, pp 484-495, issn 1045-9227Article

generalised approach to automatic custom layout of analogue ICsCHEN, D. J; SHEU, B. J.IEE proceedings. Part G. Circuits devices and systems. 1992, Vol 139, Num 4, pp 481-490, issn 0956-3768Article

Hardware annealing in electronic neural networksLEE, B. W; SHEU, B. J.IEEE transactions on circuits and systems. 1991, Vol 38, Num 1, pp 134-137, issn 0098-4094, 4 p.Article

New method for determination of geometric dependences of submicrometre MOS transistor parametersWAN, C. P; SHEU, B. J.IEE proceedings. Part G. Electronic circuits and systems. 1990, Vol 137, Num 4, pp 275-278, issn 0143-7089Article

Computer-aided VLSI circuit reliability assuranceWEN-JAY HSU; SHEU, B. J; TYREE, V. C et al.International journal of modelling & simulation. 1989, Vol 9, Num 4, pp 118-123, issn 0228-6203, 6 p.Article

A compact neural-network-based CDMA receiverCHEN, D. C; SHEU, B. J.IEEE transactions on circuits and systems. 2, Analog and digital signal processing. 1998, Vol 45, Num 3, pp 384-387, issn 1057-7130Article

A CDMA communication detector with robust near-far resistance using paralleled array processorsCHEN, D. C.-H; SHEU, B. J; YOUNG, W. C et al.IEEE transactions on circuits and systems for video technology. 1997, Vol 7, Num 4, pp 654-662, issn 1051-8215Article