RELIABILITY MODELING OF COMPENSATING MODULE FAILURES IN MAJORITY VOTED REDUNDANCY.SIEWIOREK DP.1975; I.E.E.E. TRANS. COMPUTERS; U.S.A.; DA. 1975; VOL. 24; NO 5; PP. 525-533; BIBL. 12 REF.Article

SYNCHRONIZATION AND VOTINGMCCONNEL SR; SIEWIOREK DP.1981; IEEE TRANS. COMPUT.; ISSN 0018-9340; USA; DA. 1981; VOL. 30; NO 2; PP. 161-164; BIBL. 7 REF.Article

RELIABILITY AND PERFORMANCE OF ERROR-CORRECTING MEMORY AND REGISTER ARRAYSELKIND SA; SIEWIOREK DP.1980; IEEE TRANS. COMPUT.; ISSN 0018-9340; USA; DA. 1980; VOL. 29; NO 10; PP. 920-927; BIBL. 11 REF.Article

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MEASURING DESIGNER PERFORMANCE TO VERIFY DESIGN AUTOMATION SYSTEMSTHOMAS DE; SIEWIOREK DP.1981; IEEE TRANS. COMPUT.; ISSN 0018-9340; USA; DA. 1981; VOL. 30; NO 1; PP. 48-61; BIBL. 21 REF.Article

RELIABILITY MODELS FOR MULTIPROCESSOR SYSTEMS WITH AND WITHOUT PERIODIC MAINTENANCE.INGLE AD; SIEWIOREK DP.1977; IN: FTCS-7. ANNU. INT. CONF. FAULT-TOLERANT COMPUT. 7; LOS ANGELES; 1977; NEW YORK; INST ELECTR. ELECTRON. ENG.; DA. 1977; PP. 3-9; BIBL. 8 REF.Conference Paper

A RELIABILITY MODEL FOR VARIOUS SWITCH DESIGNS IN HYBRID REDUNDANCY.INGLE AD; SIEWIOREK DP.1976; I.E.E.E. TRANS. COMPUTERS; U.S.A.; DA. 1976; VOL. 25; NO 2; PP. 115-133; BIBL. 14 REF.Article

AN ALGORITHM FOR THE ACCURATE RELIABILITY EVALUATION OF TRIPLE MODULAR REDUNDANCY NETWORKS.ABRAHAM JA; SIEWIOREK DP.1974; I.E.E.E. TRANS. COMPUTERS; U.S.A.; DA. 1974; VOL. 23; NO 7; PP. 682-692; BIBL. 20 REF.Article

SWITCH COMPLEXITY IN SYSTEMS WITH HYBRID REDUNDANCYSIEWIOREK DP; MCCLUSKEY EJ.1973; I.E.E.E. TRANS. COMPUTERS; U.S.A.; DA. 1973; VOL. 22; NO 3; PP. 276-282; BIBL. 13 REF.Serial Issue

THE CMURT-CAD SYSTEM. AN INNOVATIVE APPROACH TO COMPUTER AIDED DESIGN.SIEWIOREK DP; BARBACCI MR.1976; IN: NATL. COMPUT. CONF. PROC.; NEW YORK, N.Y.; 1976; MONTVALE, N.J.; AM. FED. INF. PROCESS. SOC.; DA. 1976; PP. 643-655; BIBL. 14 REF.Conference Paper

TEACHING WITH A HIERARCHICALLY STRUCTURED DIGITAL SYSTEMS LABORATORY.GRASON J; SIEWIOREK DP.1975; COMPUTER; U.S.A.; DA. 1975; VOL. 8; NO 12; PP. 73-81; BIBL. 5 REF.Article

AN ITERATIVE CELL SWITCH DESIGN FOR HYBRID REDUNDANCYSIEWIOREK DP; MCCLUSKEY EJ.1973; I.E.E.E. TRANS. COMPUTERS; U.S.A.; DA. 1973; VOL. 22; NO 3; PP. 290-297; BIBL. 14 REF.Serial Issue

THE MEASUREMENT AND ANALYSIS OF TRANSIENT ERRORS IN DIGITAL COMPUTER SYSTEMSMCCONNEL SR; SIEWIOREK DP; TSAO MM et al.1979; FTCS-9. ANNUAL INTERNATIONAL SYMPOSIUM ON FAULT-TOLERANT COMPUTING. 9/1979/MADISON WI; USA; NEW YORK: IEEE; DA. 1979; PP. 67-70; BIBL. 10 REF.Conference Paper

TESTING OF DIGITAL SYSTEMSSIEWIOREK DP; KWOK WOON LAI L.1981; PROC. IEEE; ISSN 0018-9219; USA; DA. 1981; VOL. 69; NO 10; PP. 1321-1333; BIBL. 42 REF.Article

A SURVEY OF HIGHLY PARALLEL COMPUTINGHAYNES LS; LAU RL; SIEWIOREK DP et al.1982; COMPUTER; ISSN 0018-9162; USA; DA. 1982; VOL. 15; NO 1; PP. 9-24; BIBL. 94 REF.Article

COMMENTS ON "MULTIPLE FAULT DETECTION IN COMBINATIONAL NETWORKS".GEOL P; SIEWIOREK DP; GAUT JW et al.1974; I.E.E.E. TRANS. COMPUTERS; U.S.A.; DA. 1974; VOL. 23; NO 3; PP. 333-334Article