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Improved sensing scheme for FeRAMJINGHUA ZHANG; JINFENG KANG; SHUZUO LOU et al.Microelectronic engineering. 2003, Vol 66, Num 1-4, pp 695-700, issn 0167-9317, 6 p.Conference Paper

Decreasing energy consumption in address decoders by means of selective precharge schemesTURI, Michael A; DELGADO-FRIAS, José G.Microelectronics journal. 2009, Vol 40, Num 11, pp 1592-1602, issn 0959-8324, 11 p.Conference Paper

Low-Voltage Embedded NAND-ROM Macros Using Data-Aware Sensing Reference Scheme for VDDmin, Speed and Power ImprovementYANG, Shu-Meng; CHANG, Meng-Fan; CHIANG, Chi-Chuang et al.IEEE journal of solid-state circuits. 2013, Vol 48, Num 2, pp 611-623, issn 0018-9200, 13 p.Article

An On-Chip Test Structure and Digital Measurement Method for Statistical Characterization of Local Random Variability in a ProcessMUKHOPADHYAY, Saibal; KIM, Keunwoo; JENKINS, Keith A et al.IEEE journal of solid-state circuits. 2008, Vol 43, Num 9, pp 1951-1963, issn 0018-9200, 13 p.Article

A Low-Voltage Bulk-Drain-Driven Read Scheme for Sub-0.5 V 4 Mb 65 nm Logic-Process Compatible Embedded Resistive RAM (ReRAM) MacroCHANG, Meng-Fan; WU, Che-Wei; KUO, Chia-Cheng et al.IEEE journal of solid-state circuits. 2013, Vol 48, Num 9, pp 2250-2259, issn 0018-9200, 10 p.Article

A Sensing Noise Compensation Bit Line Sense Amplifier for Low Voltage ApplicationsMYOUNG JIN LEE.IEEE journal of solid-state circuits. 2011, Vol 46, Num 3, pp 690-694, issn 0018-9200, 5 p.Article

A mechanism for asymmetric data writing failureMYOUNG JIN LEE; KUN WOO PARK.Solid-state electronics. 2011, Vol 56, Num 1, pp 211-213, issn 0038-1101, 3 p.Article

A 300 MHz Embedded Flash Memory with Pipeline Architecture and Offset-Free Sense Amplifiers for Dual-Core Automotive Microcontrollers : Hardware and software technologies on advanced microprocessorsKAJIYAMA, Shinya; FUJITO, Masamichi; KASAI, Hideo et al.IEICE transactions on electronics. 2009, Vol 92, Num 10, pp 1258-1264, issn 0916-8524, 7 p.Article

Robust SRAM Design via BIST-Assisted Timing-Tracking (BATT)LAI, Ya-Chun; HUANG, Shi-Yu.IEEE journal of solid-state circuits. 2009, Vol 44, Num 2, pp 642-649, issn 0018-9200, 8 p.Article

Position dependent measurement of single event transient voltage pulse shapes under heavy ion irradiationSCHWEIGER, K; HOFBAUER, M; DIETRICH, H et al.Electronics letters. 2012, Vol 48, Num 3, pp 171-172, issn 0013-5194, 2 p.Article

Self-blocking flip-flop designLI, X; JIA, S; LIANG, X et al.Electronics letters. 2012, Vol 48, Num 2, pp 82-83, issn 0013-5194, 2 p.Article

A high-speed, small-area, threshold-voltage-mismatch compensation sense amplifier for gigabit-scale DRAM arraysKAWAHARA, T; SAKATA, T; ITOH, K et al.IEEE journal of solid-state circuits. 1993, Vol 28, Num 7, pp 816-823, issn 0018-9200Conference Paper

A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group RestrictionOH, Tae-Young; SOHN, Young-Soo; KIM, Jin-Hyun et al.IEEE journal of solid-state circuits. 2011, Vol 46, Num 1, pp 107-118, issn 0018-9200, 12 p.Conference Paper

Fast Low Power eDRAM Hierarchical Differential Sense AmplifierSCHUSTER, Stanley E; MATICK, Richard E.IEEE journal of solid-state circuits. 2009, Vol 44, Num 2, pp 631-641, issn 0018-9200, 11 p.Article

A Current-Mirror Winner-Take-All Sense Amplifier for Low Voltage SRAMsJIA, Song; XU, Heqing; WU, Fengfeng et al.IEICE transactions on electronics. 2013, Vol 96, Num 9, pp 1205-1207, issn 0916-8524, 3 p.Article

A 90 nm-CMOS, 500 Mbps, 3―5 GHz Fully-Integrated IR-UWB Transceiver With Multipath Equalization Using Pulse Injection-Locking for Receiver Phase SynchronizationCHANGHUI HU; KHANNA, Rahul; NEJEDLO, Jay et al.IEEE journal of solid-state circuits. 2011, Vol 46, Num 5, pp 1076-1088, issn 0018-9200, 13 p.Conference Paper

0.5-V Low-VT CMOS Preamplifier for Low-Power and High-Speed Gigabit-DRAM ArraysKOTABE, Akira; YANAGAWA, Yoshimitsu; AKIYAMA, Satoru et al.IEEE journal of solid-state circuits. 2010, Vol 45, Num 11, pp 2348-2355, issn 0018-9200, 8 p.Conference Paper

Asynchronous Computing in Sense Amplifier-Based Pass Transistor Logic : Asynchronous Circuits and SystemsLIU, Tsung-Te; ALARCON, Louis P; PIERSON, Matthew D et al.IEEE transactions on very large scale integration (VLSI) systems. 2009, Vol 17, Num 7, pp 883-892, issn 1063-8210, 10 p.Article

Design of Asynchronous Multi-Bit OTP MemoryCHOI, Chul-Ho; LEE, Jae-Hyung; KIM, Tae-Hoon et al.IEICE transactions on electronics. 2009, Vol 92, Num 1, pp 173-177, issn 0916-8524, 5 p.Article

A 0.13 μm 8 Mb Logic-Based CuxSiyO ReRAM With Self-Adaptive Operation for Yield Enhancement and Power ReductionXIAOYONG XUE; WENXIANG JIAN; JINGANG WU et al.IEEE journal of solid-state circuits. 2013, Vol 48, Num 5, pp 1315-1322, issn 0018-9200, 8 p.Article

Optimisation design for EEPROM embedded in UHF-RFID passive transpondersMING LI; YANG, Li-Wu; KANG, Jin-Feng et al.International journal of electronics. 2011, Vol 98, Num 4-6, pp 569-582, issn 0020-7217, 14 p.Article

A Low-Power Level-Converting Double-Edge-Triggered Flip-Flop DesignWANG, Li-Rong; LO, Kai-Yu; JOU, Shyh-Jye et al.IEICE transactions on electronics. 2013, Vol 96, Num 10, pp 1351-1355, issn 0916-8524, 5 p.Article

Power-Efficient Explicit-Pulsed Dual-Edge Triggered Sense-Amplifier Flip-FlopsMYINT WAI PHYU; KANGKANG FU; WANG LING GOH et al.IEEE transactions on very large scale integration (VLSI) systems. 2011, Vol 19, Num 1, pp 1-9, issn 1063-8210, 9 p.Article

Energy-Delay Performance of Nanoscale Transistors Exhibiting Single Electron Behavior and Associated Logic CircuitsSARIPALLI, Vinay; LU LIU; DATTA, Suman et al.Journal of low power electronics (Print). 2010, Vol 6, Num 3, pp 415-428, issn 1546-1998, 14 p.Article

A High-Density 45 nm SRAM Using Small-Signal Non-Strobed Regenerative SensingVERMA, Naveen; CHANDRAKASAN, Anantha P.IEEE journal of solid-state circuits. 2009, Vol 44, Num 1, pp 163-173, issn 0018-9200, 11 p.Conference Paper

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