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Behavioral to structural translation in a bit-serial silicon compilerHARTLEY, R. I; JASICA, J. R.IEEE transactions on computer-aided design of integrated circuits and systems. 1988, Vol 7, Num 8, pp 877-886, issn 0278-0070Article

Test de cartes: La génération non spontanée = Card testing: and spontaneous generationFORGUE, B.Mesures (1983). 1988, Vol 53, Num 8, pp 47-52, issn 0755-219X, 4 p.Article

Modélisation numérique du comportement électrique des interconnexions en technologie multicouche haute densité = Numerical modelling of electrical behavior of interconnections in high density multilayered technologyMoulondo, Jean-Claude; Touboul, A.1994, 150 p.Thesis

Timing macromodels for CMOS static set/reset latches and their applicationsWU, C.-Y; LI, C; HWANG, J. S et al.IEE proceedings. Part E. Computers and digital techniques. 1988, Vol 135, Num 3, pp 151-160, issn 0143-7062Article

Generation of performance constraints for layoutRAVI NAIR; BERMAN, C. L; HAUGE, P. S et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1989, Vol 8, Num 8, pp 860-874, issn 0278-0070Article

Lignes d'interconnexions pour circuits logiques rapides : traitement temporel du couplage et des pertesZounon, Arimyaou; Adde, Robert.1989, 282 p.Thesis

LSI gate arrays, MSIS and SRAMsGONAUSER, E; KÖSLER, E; RAUSCHERT, R et al.Siemens Forschungs- und Entwicklungsberichte. 1988, Vol 17, Num 5, pp 215-220, issn 0370-9736Article

Modélisation et caractérisation des signaux logiques CMOS = Modeling and characterisation of CMOS logical signalsSirot, Isabelle; Demassieux, N.1995, 192 p.Thesis

Contribution au développement du compilateur structurel PRINT : algorithmes d'évaluation des performances temporelles des structures CMOSRobert, Michel; Auvergne, D.1987, 160 p.Thesis

An approach to the formal verification of VHDL descriptionsBORRIONE, D; PAILLET, J. L.Rapport de recherche - IMAG. 1987, Vol 683, issn 0750-7380, 21 p.Report

ICCAD 86 : a conference for the EE CAD professional, Santa Clara CA, November 11-13 1986International conference on computer-aided design. 1986, XXXII-523 p, isbn 0-8186-0744-0Conference Proceedings

Modélisation fréquentielle et performance temporelle des interconnexions de circuits intégrés silicium = Frequency modeling and time performance of silicon integrated circuits connectionsCHILO, Jean.1986, 24 p.Report

INFLUENCE DES FACTEURS TEMPORELS SUR LE COMPORTEMENT FONCTIONNEL D'UN CIRCUIT L.S.I.CHICOIX C; PEDOUSSAT J; THUEL J et al.1974; DGRST-7371391; FR.; DA. 1974; PP. 1-208; (RAPP. FINAL, ACTION CONCERTEE: C.C.M.)Report

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