Oxide traps characterization of 45 nm MOS transistors by gate current R.T.S. noise measurementsMARTINEZ, F; LEYRIS, C; BARGE, D et al.Microelectronic engineering. 2005, Vol 80, pp 54-57, issn 0167-9317, 4 p.Conference Paper

Ultra-low cost and high performance 65nm CMOS device fabricated with plasma dopingLALLEMENT, F; DURIEZ, B; GODET, L et al.Symposium on VLSI Technology. sd, pp 178-179, isbn 0-7803-8289-7, 1Vol, 2 p.Conference Paper

New concept of high-k integration in MOSFET's by a deposition through contact holesHARRISON, S; CORONEL, P; WACQUANT, F et al.Microelectronic engineering. 2004, Vol 72, Num 1-4, pp 321-325, issn 0167-9317, 5 p.Conference Paper

Poly-gate REplacement through contact hole (PRETCH) : A new method for high-k/metal gate and multi-oxide implementation on chipHARRISON, S; CORONEL, P; BARGE, D et al.International Electron Devices Meeting. 2004, pp 291-294, isbn 0-7803-8684-1, 1Vol, 4 p.Conference Paper

65 nm LP/GP mix low cost platform for multi-media wireless and consumer applicationsTAVEL, B; DURIEZ, B; BOEUF, F et al.Solid-state electronics. 2006, Vol 50, Num 4, pp 573-578, issn 0038-1101, 6 p.Conference Paper

A conventional 45nm CMOS node low-cost platform for general purpose and low power applicationsBOEUF, F; ARNAUD, F; PAIN, L et al.International Electron Devices Meeting. 2004, pp 425-428, isbn 0-7803-8684-1, 1Vol, 4 p.Conference Paper

Gate stack optimization for 65nm CMOS Low Power and High Performance platformDURIEZ, B; TAVEL, B; PALLA, R et al.International Electron Devices Meeting. 2004, pp 847-850, isbn 0-7803-8684-1, 1Vol, 4 p.Conference Paper

Amplitude regulation of vocalizations in noise by a songbird, Taeniopygia guttataCYNX, J; LEWIS, R; TAVEL, B et al.Animal behaviour. 1998, Vol 56, pp 107-113, issn 0003-3472, 1Article

New hole trapping characterization during NBTI in 65nm node technology with distinct nitridation processingDENAIS, M; BRAVAIX, A; PERRIER, F et al.International Integrated Reliability Workshop. 2004, pp 121-124, isbn 0-7803-8517-9, 1Vol, 4 p.Conference Paper

New metal gate architecture achieved by chemical vapor deposition for a complete tunnel fillREGNIER, C; WACQUANT, F; LEVERD, F et al.Proceedings - Electrochemical Society. 2003, pp 391-396, issn 0161-6374, isbn 1-56677-396-2, 6 p.Conference Paper

High performance 40nm nMOSFETs with HfO₂ gate dielectric and polysilicon damascene gateTAVEL, B; GARROS, X; LEVERD, F et al.IEDm : international electron devices meeting. 2002, pp 429-432, isbn 0-7803-7462-2, 4 p.Conference Paper

SON (Silicon-On-Nothing) P-MOSFETs with totally silicided (CoSi₂) polysilicon on 5nm-thick Si-films: The simplest way to integration of metal gates on thin FD channelsMONFRAY, S; SKOTNICKI, T; LEVERD, F et al.IEDm : international electron devices meeting. 2002, pp 263-266, isbn 0-7803-7462-2, 4 p.Conference Paper

Low cost 65nm CMOS platform for low power & general purpose applicationsARNAUD, F; DURIEZ, B; REYNARD, J. P et al.Symposium on VLSI Technology. sd, pp 10-11, isbn 0-7803-8289-7, 1Vol, 2 p.Conference Paper