au.\*:("TOMISAKA, Manabu")
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Copper electrodeposition of high-aspect-ratio vias for three dimensional packagingKONDO, Kazuo; YONEZAWA, Toshihiro; TOMISAKA, Manabu et al.Proceedings - Electrochemical Society. 2003, pp 28-32, issn 0161-6374, isbn 1-56677-390-3, 5 p.Conference Paper
Cu bump interconnections in 20 μm-pitch at low temperature utilizing electroless tin-plating on 3D stacked LSITOMITA, Yoshihiro; MORIFUJI, Tadahiro; TOMISAKA, Manabu et al.Journal of chemical engineering of Japan. 2003, Vol 36, Num 2, pp 119-125, issn 0021-9592, 7 p.Article
Process integration of 3D chip stack with vertical interconnectionTAKAHASHI, Kenji; TAGUCHI, Yuichi; UMEMOTO, Mitsuo et al.Proceedings - Electronic Components Conference. 2004, issn 0569-5503, isbn 0-7803-8365-6, 2Vol, Vol 1, 601-609Conference Paper
Development of wafer thinning and double-sided bumping technologies for the three-dimensional stacked LSISUNOHARA, Masahiro; FUJII, Tomonori; HOSHINO, Masataka et al.Proceedings - Electronic Components Conference. 2002, pp 238-245, issn 0569-5503, isbn 0-7803-7430-4, 8 p.Conference Paper
High-aspect-ratio copper via filling used for three-dimensional chip stackingSUN, Jian-Jun; KONDO, Kazuo; OKAMURA, Takuji et al.Journal of the Electrochemical Society. 2003, Vol 150, Num 6, pp G355-G358, issn 0013-4651Article
Electroplating Cu fillings for through-vias for three-dimensional chip stackingTOMISAKA, Manabu; YONEMURA, Hitoshi; HOSHINO, Masataka et al.Proceedings - Electronic Components Conference. 2002, pp 1432-1438, issn 0569-5503, isbn 0-7803-7430-4, 7 p.Conference Paper