Effect of off-axis implant on the characteristics of advanced self-aligned bipolar transistorsCHING-TE CHUANG; LI, G. P; NING, T. H et al.IEEE electron device letters. 1987, Vol 8, Num 7, pp 321-323, issn 0741-3106Article

Below 10 ps/gate operation with buried p-layer SAINT FETsYAMASAKI, K; KATO, N; HIRAYAMA, M et al.Electronics Letters. 1984, Vol 20, Num 25-26, pp 1029-1031, issn 0013-5194Article

On the punchthrough characteristics of advanced self-aligned bipolar transistorsCHUANG, C. T; DUAN-LEE TANG, D; LI, G. P et al.I.E.E.E. transactions on electron devices. 1987, Vol 34, Num 7, pp 1519-1524, issn 0018-9383Article

Symmetric-gain, zero-offset, self-aligned, and refractory-contact double HBT'sTIWARI, S; WRIGHT, S. L.IEEE electron device letters. 1987, Vol 8, Num 9, pp 417-420, issn 0741-3106Article

Novel process for emitter-base-collector self-aligned heterojunction bipolar transistor using a pattern-inversion methodTANAKA, S; MADIHIAN, M; TOYOSHIMA, H et al.Electronics Letters. 1987, Vol 23, Num 11, pp 562-564, issn 0013-5194Article

Fin width scaling criteria of body-tied FinFET in sub-50 nm regimeHYE JIN CHO; JEONG DONG CHOE; MING LI et al.DRC : Device research conference. 2004, pp 209-210, isbn 0-7803-8284-6, 1Vol, 2 p.Conference Paper

Bulk inversion in FinFETs and the implied insignificance of the effective gate widthKIM, S.-H; FOSSUM, J. G; TRIVEDI, V. P et al.IEEE international SOI conference. 2004, pp 145-147, isbn 0-7803-8497-0, 1Vol, 3 p.Conference Paper

Emitter-base-collector self-aligned heterojunction bipolar transistors using wet etching processEDA, K; INADA, M; OTA, Y et al.IEEE electron device letters. 1986, Vol 7, Num 12, pp 694-696, issn 0741-3106Article

Effects of GaAs/AlAs superlattice buffer layers on selective area regrowth for GaAs/AlGaAs self-aligned structure lasersNODA, S; FUJIWARA, K; NAKAYAMA, T et al.Applied physics letters. 1985, Vol 47, Num 11, pp 1205-1207, issn 0003-6951Article

Two-dimensional effects in the bipolar polysilicon self-aligned transistorVERRET, D. P; BRIGHTON, J. E.I.E.E.E. transactions on electron devices. 1987, Vol 34, Num 11, pp 2297-2303, issn 0018-9383Article

Low-resistance submicrometre gates used for self alignmentISMAIL, K; BENEKING, H.Electronics Letters. 1984, Vol 20, Num 22, pp 942-943, issn 0013-5194Article

A lateral silicon-on-insulator bipolar transistor with a self-aligned base contactSTURM, J. C; MCVITTIE, J. P; GIBBONS, J. F et al.IEEE electron device letters. 1987, Vol 8, Num 3, pp 104-106, issn 0741-3106Article

Metal-oxide-semiconductor field-effect transistors fabricated using self-aligned silicide technologyTSAUR, B.-Y; ANDERSON, C. H. JR.Applied physics letters. 1985, Vol 47, Num 5, pp 527-529, issn 0003-6951Article

Self-alignment a-Si FET by using a lift-off techniqueOKADA, H; UCHIDA, Y; WATANABE, Y et al.Electronics Letters. 1985, Vol 21, Num 15, pp 633-634, issn 0013-5194Article

Characteristics of sub-half-micrometre-gate self-aligned GaAs FET by ion implantationMATSUMOTO, K; HASHIZUME, N; ATODA, N et al.Electronics Letters. 1984, Vol 20, Num 22, pp 940-942, issn 0013-5194Article

Identification and implication of a perimeter tunneling current component in advanced self-aligned bipolar transistorsLI, G. P; HACKBARTH, E; TZE-CHIANG CHEN et al.I.E.E.E. transactions on electron devices. 1988, Vol 35, Num 1, pp 89-95, issn 0018-9383Article

A new MOSFET structure with self aligned polysilicon and drain electrodesOH, C. S; KIM, C. K.IEEE electron device letters. 1984, Vol 5, Num 10, pp 400-402, issn 0741-3106Article

The Important Challenge to Extend Spacer DP process towards 22nm and beyondOYAMA, Kenichi; NISIMURA, Eiichi; YAMAJI, Tomohito et al.Proceedings of SPIE, the International Society for Optical Engineering. 2010, Vol 7639, issn 0277-786X, isbn 978-0-8194-8053-8 0-8194-8053-3, 763907.1-763907.6, 2Conference Paper

Improved self-aligned structure for GaAlAs high-power lasersYOSHIZAWA, M; UOMI, K; OHISHI, A et al.Japanese journal of applied physics. 1987, Vol 26, Num 9, pp L1465-L1467, issn 0021-4922, 2Article

High yield reduced process tolerance self-aligned double mesa process technology for SiGe power HBTsLEE, Kok-Yan; JOHNSON, Brian N; MOHAMMADI, Saeed et al.IEEE MTT-S International Microwave Symposium. 2004, isbn 0-7803-8331-1, vol2, 963-966Conference Paper

Au/TaN/WN/GaAs structure Schottky gate formation for self-aligned GaAs MESFETYAMAGISHI, H; MIYAUCHI, M.Japanese journal of applied physics. 1985, Vol 24, Num 10, pp L841-L844, issn 0021-4922Article

A sub-400°C germanium MOSFET technology with high-κ dielectric and metal gateCHI ON CHUI; KIM, Hyoungsub; CHI, David et al.IEDm : international electron devices meeting. 2002, pp 437-440, isbn 0-7803-7462-2, 4 p.Conference Paper

AlGaAs/GaAs heterojunction bipolar transistors fabricated using a self-aligned dual-lift-off processCHANG, M.-C. F; ASBECK, P. M; WANG, K. C et al.IEEE electron device letters. 1987, Vol 8, Num 7, pp 303-305, issn 0741-3106Article

Cladding-mode extraction from long-period fibre grating using self-aligned core-mode blockerSUZUKI, S; ITO, H; TAKATA, Y et al.Electronics Letters. 2007, Vol 43, Num 6, pp 330-332, issn 0013-5194, 3 p.Article

Self-aligned 40 nm channel carbon nanotube field-effect transistors with subthreshold swings down to 70mV/decadeJAVEY, Ali; FARMER, Damon; GORDON, Roy et al.SPIE proceedings series. 2005, pp 14-18, isbn 0-8194-5706-X, 5 p.Conference Paper