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A novel 248-nm wet-developable BARC for trench applicationsNEEF, Charles J; THOMAS, Deborah.Proceedings of SPIE, the International Society for Optical Engineering. 2007, pp 65192Z.1-65192Z.8, issn 0277-786X, isbn 978-0-8194-6638-9Conference Paper

Experimental study and simulations on two different avalanche modes in trench power MOSFETsPAWEL, I; SIEMIENIEC, R; RÖSCH, M et al.IET circuits, devices & systems (Print). 2007, Vol 1, Num 5, pp 341-346, issn 1751-858X, 6 p.Conference Paper

Challenges for quality 15nm groove patterning with ZEP520A for a master fabrication for track pitch 50nm full-surface DTR-MediaIYAMA, Hiromasa; HAMAMOTO, Kazuhiro; KISHIMOTO, Shuji et al.Proceedings of SPIE, the International Society for Optical Engineering. 2010, Vol 7748, issn 0277-786X, isbn 0-8194-8238-2 978-0-8194-8238-9, 1Vol, 77481Z.1-77481Z.5Conference Paper

Micro projection lithography using microlens on a maskJI, Chang-Hyeon; HERRAULT, Florian; ALLEN, Mark G et al.Journal of micromechanics and microengineering (Print). 2009, Vol 19, Num 12, issn 0960-1317, 127003.1-127003.6Article

Fabrication and characterization of gated carbon nanotube emitters in a trench structureLIAO, Y. F; SHE, J. C; HE, H et al.International Vacuum Nanoelectronics Conference. 2004, pp 66-67, isbn 0-7803-8397-4, 1Vol, 2 p.Conference Paper

Using trenches to reduce tunnelling vibrationsRAHMAN, M. E; ORR, T. L. L.Proceedings of the Institution of Civil Engineers - Geotechnical engineering. 2008, Vol 161, Num 5, pp 227-233, issn 1353-2618, 7 p.Article

A multi trench analog+logic protection (M-TRAP) for substrate crosstalk prevention in a 0.25μm smart power platform with 100V high-side capabilityPARTHASARATHY, V; KHEMKA, V; ZHU, R et al.International Symposium on Power Semiconductor Devices & ICs. 2004, pp 427-430, isbn 4-88686-060-5, 4 p.Conference Paper

On-chip isolation in wafer-level chip-scale packages: Substrate thinning and circuit partitioning by trenchesSINAGA, S. M; POLYAKOV, A; BARTEK, M et al.SPIE proceedings series. 2003, pp 768-773, isbn 0-8194-5189-4, 6 p.Conference Paper

New trencher makes Troll inaugurationOffshore technology. 2000, Vol 8, Num 4, pp 27-30, 2 p.Article

MOS controlled diodes : a new power diodeQIN HUANG; AMARATUNGA, G. A. J.Solid-state electronics. 1995, Vol 38, Num 5, pp 977-980, issn 0038-1101Article

Silicide/high-k dielectric structures for nanotransistor gatesHORIN, I. A; KRIVOSPITSKY, A. D; ORLIKOVSKY, A. A et al.Proceedings of SPIE, the International Society for Optical Engineering. 2006, pp 62600G.1-62600G.8, issn 0277-786X, isbn 0-8194-6325-6, 1VolConference Paper

On increasing the accuracy of simulations of deposition and etching processes using radiosity and the level set methodHEITZINGER, Clemens; FUGGER, Josef; SELBERHERR, Siegfried et al.ESSCIRC 2002 : European solid-state circuits conferenceEuropean solid-state device research conference. 2002, pp 347-350, isbn 88-900847-8-2, 4 p.Conference Paper

Strategies and test structures for improving isolation between circuit blocksSZMYD, David; GAMBUS, Laurent; WILBANKS, William et al.2002 international conference on microelectronic test structures. 2002, pp 89-93, isbn 0-7803-7464-9, 5 p.Conference Paper

A high accuracy resonant pressure sensor by fusion bonding and trench etchingWELHAM, C. J; GREENWOOD, J; BERTIOLI, M. M et al.Sensors and actuators. A, Physical. 1999, Vol 76, Num 1-3, pp 298-304, issn 0924-4247Conference Paper

Three-additive model of superfilling of copperYANG CAO; TAEPHAISITPHONGSE, Premratn; CHALUPA, Radek et al.Journal of the Electrochemical Society. 2001, Vol 148, Num 7, pp C466-C472, issn 0013-4651Article

Characterization of tungsten silicide (WSix) films grown by chemical vapor deposition (CVD)HOSSAIN, F; AMBADI, S; WINER, R et al.SPIE proceedings series. 1999, pp 58-61, isbn 0-8194-3478-7Conference Paper

Failure analysis and improvement of 60 V power UMOSFETWANG DEBO; FENG QUANYUAN; CHEN XIAOPEI et al.Microelectronics and reliability. 2014, Vol 54, Num 12, pp 2782-2787, issn 0026-2714, 6 p.Article

Investigation of power Trench MOSFETs with retrograde body profileWANG YING; CHENG CHAO; HU, Hai-Fan et al.Microelectronics and reliability. 2011, Vol 51, Num 2, pp 513-516, issn 0026-2714, 4 p.Article

Exploring Complex 2D Layouts for 22 nm Node Using Double Patterning / Double Etch Approach for Trench LevelsJESSEN, Scott W; PRINS, Steve L; BLATCHFORD, James W et al.Proceedings of SPIE, the International Society for Optical Engineering. 2010, Vol 7641, issn 0277-786X, isbn 978-0-8194-8055-2 0-8194-8055-X, 76410A.1-76410A.12Conference Paper

Double Patterning Process with Freezing TechniqueWAKAMATSU, Goji; ANNO, Yusuke; SHIMOKAWA, Tsutomu et al.Proceedings of SPIE, the International Society for Optical Engineering. 2009, Vol 7273, issn 0277-786X, isbn 978-0-8194-7526-8 0-8194-7526-2, 72730B.1-72730B.8, 2Conference Paper

Role of abrasives in high selectivity STI CMP slurriesMANIVANNAN, R; RAMANATHAN, S.Microelectronic engineering. 2008, Vol 85, Num 8, pp 1748-1753, issn 0167-9317, 6 p.Article

Optical properties of alternating phase-shifting masksGLEASON, Bob; CHENG, Wen-Hao.Proceedings of SPIE, the International Society for Optical Engineering. 2006, pp 63491B.1-63491B.10, issn 0277-786X, isbn 0-8194-6444-9, 2VolConference Paper

Determination of process margin and global planarization characteristics in the direct STI-CMP processSEO, Yong-Jin; KIM, Sang-Yong.Journal of materials science. Materials in electronics. 2004, Vol 15, Num 6, pp 363-367, issn 0957-4522, 5 p.Article

Fabrication of step and flash imprint lithography templates using a variable shaped-beam exposure toolDAUKSHER, William J; MANCINI, David; NORDQUIST, Kevin et al.Microelectronic engineering. 2004, Vol 75, Num 4, pp 345-351, issn 0167-9317, 7 p.Article

Record low specific on-resistance for low-voltage trench MOSFETsIN'T ZANDT, M. A. A; HIJZEN, E. A; HUETING, R. J. E et al.IEE proceedings. Circuits, devices and systems. 2004, Vol 151, Num 3, pp 269-272, issn 1350-2409, 4 p.Conference Paper

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