A dual-band 802.11a/b/g radio in 0.18μm CMOSPERRAUD, L; PINATEL, C; RECOULY, M et al.IEEE International Solid-State Circuits Conference. 2004, pp 94-95, isbn 0-7803-8267-6, 2Vol, 2 p.Conference Paper

Characterization of poly-buffered LOCOS in manufacturing environmentGULDI, R. L; MCKEE, B; DAMMINGA, G. M et al.Journal of the Electrochemical Society. 1989, Vol 136, Num 12, pp 3815-3820, issn 0013-4651, 6 p.Article

2-to-1 selector IC in 90-nm CMOS technology operating up to 50 Gb/sYAMAMOTO, Takuji; YAMAZAKI, Daisuke; HORINAKA, Minoru et al.IEEE Compound Semiconductor Integrated Circuit Symposium. 2004, pp 243-246, isbn 0-7803-8616-7, 1Vol, 4 p.Conference Paper

Dynamics of heavy-ion-induced latchup in CMOS structuresAOKI, T.I.E.E.E. transactions on electron devices. 1988, Vol 35, Num 11, pp 1885-1891, issn 0018-9383, 1Article

CMOS scaling theory : Why our theory of everything still works, and what that means for the futureFOTY, Daniel; GILDENBLAT, Gennady.IEEE international symposium on electron devices for microwave and optoelectronic applications. 2004, pp 27-38, isbn 0-7803-8574-8, 1Vol, 12 p.Conference Paper

A four-channel ADSL2+ analog front end for CO applications with 75mW per channel built in 0.13μm cmosPESSL, Peter; HOHL, Johannes; GAGGL, Richard et al.IEEE International Solid-State Circuits Conference. 2004, pp 402-403, isbn 0-7803-8267-6, 2Vol, 2 p.Conference Paper

Variability reduction in CMOS operational amplifiers through layout modificationBHATTACHARYYA, A. B; AGGARWAL, S.IEE proceedings. Part G. Electronic circuits and systems. 1989, Vol 136, Num 2, pp 79-83, issn 0143-7089, 5 p.Article

A high-performance bipolar/CMOS process―CIT2VOLZ, C; BLOSSFELD, L.I.E.E.E. transactions on electron devices. 1988, Vol 35, Num 11, pp 1861-1865, issn 0018-9383, 1Article

Analysis of a source-coupled CMOS multivibratorFINVERS, I. G; FILANOVSKY, I. M.IEEE transactions on circuits and systems. 1988, Vol 35, Num 9, pp 1182-1185, issn 0098-4094Article

On-chip timing measurement architecture with femtosecond resolutionCOLLINS, M; AL-HASHIMI, B. M; WILSON, P. R et al.Electronics Letters. 2006, Vol 42, Num 9, pp 528-530, issn 0013-5194, 3 p.Article

New materials, processes and device structures for 65nm cmos technology node and beyondNGUYEN, B.-Y; THEAN, A; VARTANIAN, V et al.Proceedings - Electrochemical Society. 2005, pp 259-273, issn 0161-6374, isbn 1-56677-463-2, 15 p.Conference Paper

A fully integrated 0.13μm CMOS 10Gb ethernet transceiver with XAUI interfaceLEE, Hyung-Rok; HWANG, Moon-Sang; LEE, Bong-Joon et al.IEEE International Solid-State Circuits Conference. 2004, pp 170-171, isbn 0-7803-8267-6, 2Vol, 2 p.Conference Paper

A 1.5V 28mA fully-integrated fast-locking quad-band GSM-GPRS transmitter with digital auto-calibration in 130nm CMOSLEE, S. T; FANG, S. J; ALLSTOT, D. J et al.IEEE International Solid-State Circuits Conference. 2004, pp 188-189, isbn 0-7803-8267-6, 2Vol, 2 p.Conference Paper

A 25GHz clock buffer and a 50Gb/s 2:1 selector in 90nm CMOSYAMAZAKI, Daisuke; YAMAMOTO, Takuji; HORINAKA, Minoru et al.IEEE International Solid-State Circuits Conference. 2004, pp 240-241, isbn 0-7803-8267-6, 2Vol, 2 p.Conference Paper

High-speed CMOS circuit techniqueYUAN, J; SVENSSON, C.IEEE journal of solid-state circuits. 1989, Vol 24, Num 1, pp 62-70, issn 0018-9200, 9 p.Article

Reverse-voltage protection methods for CMOS circuitsBRUUN, E.IEEE journal of solid-state circuits. 1989, Vol 24, Num 1, pp 100-103, issn 0018-9200, 4 p.Article

Si-gate CMOS devices on a Si lateral solid-phase epitaxial layerHIRASHITA, N; KATOH, T; ONODA, H et al.I.E.E.E. transactions on electron devices. 1989, Vol 36, Num 3, pp 548-552, issn 0018-9383, 5 p.Article

Speed comparison of digital BICMOS and CMOS circuitsROTHERMEL, A; HOSTICKA, B.IEE proceedings. Part G. Electronic circuits and systems. 1989, Vol 136, Num 2, pp 49-56, issn 0143-7089, 8 p.Article

Advanced CMOS devices: Part I conventional devices and technology optionsWONG, H.-S. Philip.Proceedings - Electrochemical Society. 2005, pp 3-12, issn 0161-6374, isbn 1-56677-463-2, 10 p.Conference Paper

A CMOS dual-band fractional-N synthesizer with reference doubler and compensated charge pumpHUH, Hyungki; KOO, Yido; KIM, Wonchan et al.IEEE International Solid-State Circuits Conference. 2004, pp 100-101, isbn 0-7803-8267-6, 2Vol, 2 p.Conference Paper

Designing outside rail constraintsANNEMA, Anne-Johan; NAUTA, Bram; VAN LANGEVELDE, Ronald et al.IEEE International Solid-State Circuits Conference. 2004, pp 134-135, isbn 0-7803-8267-6, 2Vol, 2 p.Conference Paper

A new criterion for transient latchup analysis in bulk CMOSYEU-HAW YANG; CHUNG-YU WU.I.E.E.E. transactions on electron devices. 1989, Vol 36, Num 7, pp 1336-1347, issn 0018-9383, 12 p.Article

Fully symmetric cooled CMOS on (110) planeAOKI, M; YANO, K; MASUHARA, T et al.I.E.E.E. transactions on electron devices. 1989, Vol 36, Num 8, pp 1429-1433, issn 0018-9383, 5 p.Article

Metastability behavior of CMOS ASIC flip-flops in theory and testHORSTMANN, J. U; EICHEL, H. W; COATES, R. L et al.IEEE journal of solid-state circuits. 1989, Vol 24, Num 1, pp 146-157, issn 0018-9200, 12 p.Article

The effect of interconnection resistance on the performance enhancement of liquid-nitrogen-cooled CMOS circuitsWATT, J. T; PLUMMER, J. D.I.E.E.E. transactions on electron devices. 1989, Vol 36, Num 8, pp 1510-1520, issn 0018-9383, 11 p.Article