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Fin width scaling criteria of body-tied FinFET in sub-50 nm regimeHYE JIN CHO; JEONG DONG CHOE; MING LI et al.DRC : Device research conference. 2004, pp 209-210, isbn 0-7803-8284-6, 1Vol, 2 p.Conference Paper

Bulk inversion in FinFETs and the implied insignificance of the effective gate widthKIM, S.-H; FOSSUM, J. G; TRIVEDI, V. P et al.IEEE international SOI conference. 2004, pp 145-147, isbn 0-7803-8497-0, 1Vol, 3 p.Conference Paper

The Important Challenge to Extend Spacer DP process towards 22nm and beyondOYAMA, Kenichi; NISIMURA, Eiichi; YAMAJI, Tomohito et al.Proceedings of SPIE, the International Society for Optical Engineering. 2010, Vol 7639, issn 0277-786X, isbn 978-0-8194-8053-8 0-8194-8053-3, 763907.1-763907.6, 2Conference Paper

High yield reduced process tolerance self-aligned double mesa process technology for SiGe power HBTsLEE, Kok-Yan; JOHNSON, Brian N; MOHAMMADI, Saeed et al.IEEE MTT-S International Microwave Symposium. 2004, isbn 0-7803-8331-1, vol2, 963-966Conference Paper

A sub-400°C germanium MOSFET technology with high-κ dielectric and metal gateCHI ON CHUI; KIM, Hyoungsub; CHI, David et al.IEDm : international electron devices meeting. 2002, pp 437-440, isbn 0-7803-7462-2, 4 p.Conference Paper

Cladding-mode extraction from long-period fibre grating using self-aligned core-mode blockerSUZUKI, S; ITO, H; TAKATA, Y et al.Electronics Letters. 2007, Vol 43, Num 6, pp 330-332, issn 0013-5194, 3 p.Article

Self-aligned 40 nm channel carbon nanotube field-effect transistors with subthreshold swings down to 70mV/decadeJAVEY, Ali; FARMER, Damon; GORDON, Roy et al.SPIE proceedings series. 2005, pp 14-18, isbn 0-8194-5706-X, 5 p.Conference Paper

Source/drain-doping engineering for optimal nanoscale FinFET designTRIVEDI, V. P; FOSSUM, J. G.IEEE international SOI conference. 2004, pp 192-194, isbn 0-7803-8497-0, 1Vol, 3 p.Conference Paper

A novel method of fabrication of microlens arraysSIHAI CHEN; XINJIAN YI; HONG MA et al.Infrared physics & technology. 2003, Vol 44, Num 2, pp 133-135, issn 1350-4495, 3 p.Article

A self-aligned double-gate MOS transistor technology with individually addressable gatesZHANG, Shengdong; LIN, Xinnan; HUANG, Ru et al.IEEE International SOI conference. 2002, pp 207-208, isbn 0-7803-7439-8, 2 p.Conference Paper

Demonstration of 32nm half-pitch electrical testable NAND FLASH patterns using self-aligned double patterningSHIYU SUN; BENCHER, Chris; YU, James et al.Proceedings of SPIE, the International Society for Optical Engineering. 2009, Vol 7274, issn 0277-786X, isbn 978-0-8194-7527-5 0-8194-7527-0, 72740D.1-72740D.7, 2Conference Paper

Random dopant fluctuation in limited-width FinFET technologiesCHIANG, Meng-Hsueh; LIN, Jeng-Nan; KIM, Keunwoo et al.I.E.E.E. transactions on electron devices. 2007, Vol 54, Num 8, pp 2055-2060, issn 0018-9383, 6 p.Article

Novel program versus disturb window characterization for split-gate flash cellSUNG, Hung-Cheng; LEI, Tan Fu; HSU, Te-Hsun et al.IEEE electron device letters. 2005, Vol 26, Num 3, pp 194-196, issn 0741-3106, 3 p.Article

Co-silicide, Co(Ni)-silicide and Ni-silicide to source/drain contact resistanceAKHEYAR, A; LAUWERS, A; MAEX, K et al.Proceedings - Electrochemical Society. 2003, pp 197-204, issn 0161-6374, isbn 1-56677-396-2, 8 p.Conference Paper

Use of TixTiN as cap layer for the formation of cobalt silicideVULPIO, M; FAZIO, D; BILECI, M et al.Proceedings - Electrochemical Society. 2003, pp 167-173, issn 0161-6374, isbn 1-56677-390-3, 7 p.Conference Paper

LDMOS linearity and reliabilityRICE, Jed.Microwave journal (Euro-global edition). 2002, Vol 45, Num 6, pp 64-72, issn 0192-6217, 7 p.Article

Si based quasi-planar self-aligned electron emission arrayDAZHONG ZHU; JIAHUA ZHU.Applied surface science. 2002, Vol 202, Num 1-2, pp 110-113, issn 0169-4332, 4 p.Article

Multifunction SAG process for high-yield, low-cost GaAs microwave integrated circuitsBAHL, I. J; DRINKWINE, M. J; GEISSBERGER, A. E et al.IEEE transactions on microwave theory and techniques. 1990, Vol 38, Num 9, pp 1175-1182, issn 0018-9480, 8 p.Article

Multifunction small-signal chip set for transmit/receive modulesWILLEMS, D. A; COLUZZI, M. E; TANTOD, S. S et al.IEEE transactions on microwave theory and techniques. 1990, Vol 38, Num 12, pp 2007-2015, issn 0018-9480, 9 p.Article

Novel self-aligned polysilicon-gate MOSFETs with polysilicon source and drainMORAVVEJ-FARSHI, M. K; GREEN, M. A.Solid-state electronics. 1987, Vol 30, Num 10, pp 1053-1062, issn 0038-1101Article

Self-aligned-gate GaInAs microwave MISFET'sGARDNER, P. D; LIU, S. G; NARAYAN, S. Y et al.IEEE electron device letters. 1986, Vol 7, Num 6, pp 363-364, issn 0741-3106Article

Crescent Shaped Alignment Marks Applicable to Self-alignment of Micro-parts with and without Positive and Negative PolesSHIGA, Shouhei; WANG, Dong F; ISHIDA, Takao et al.Symposium on design, test, integration and packaging of MEMS-MOEMS. 2011, pp 180-183, isbn 978-2-355-00013-3, 1Vol, 4 p.Conference Paper

NP-completeness result for positive line-by-fill SADP processQIAO LI.Proceedings of SPIE, the International Society for Optical Engineering. 2010, Vol 7823, issn 0277-786X, isbn 978-0-8194-8337-9, 78233P.-78233P.11, 2Conference Paper

Spacer defined double patterning for sub-72 nm pitch logic technologyKIM, Ryoung-Han; MCLELLAN, Erin; COLBURN, Matthew E et al.Proceedings of SPIE, the International Society for Optical Engineering. 2010, Vol 7640, issn 0277-786X, isbn 978-0-8194-8054-5 0-8194-8054-1, 76400F.1-76400F.10, 2Conference Paper

The effect of lead-free solder paste on component placement accuracy and self-alignment during reflowLIUKKONEN, Timo; NUMMENPÄÄ, Pekka; TUOMINEN, Aulis et al.Soldering & surface mount technology. 2004, Vol 16, Num 1, pp 44-47, issn 0954-0911, 4 p.Article

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