Advanced gate stack, source/drain and channel engineering for Si-based CMOS : naw materials, processes, and equipment (Quebec PQ, 16-18 May 2005)Gusev, Evgeni P; Iwai, Hiroshi; Öztürk, Mehmet C et al.Proceedings - Electrochemical Society. 2005, issn 0161-6374, isbn 1-56677-463-2, XV, 634 p, isbn 1-56677-463-2Conference Proceedings

Etude de nouveaux concepts d'architectures drain-sources pour les technologies CMOS sub-0.18 microns = Study of new concepts of drain-sources architectures for sub-0.18 microns CMOS technologiesGwoziecki, Romain; Gentil, Pierre.1999, 220 p.Thesis

Artificial neural networks as aids in circuit designGANESH KOTHAPALLI.Microelectronics journal. 1995, Vol 26, Num 6, pp 569-578, issn 0959-8324Article

Growth and properties of high-quality very-thin SOS filmsDUMIN, D. J; DABRAL, S; FREYTAG, M et al.Journal of electronic materials. 1989, Vol 18, Num 1, pp 53-57, issn 0361-5235, 5 p.Article

Mismatch characterization and modelization of Deep Submicron CMOS TransistorsTHIBIEROZ, H; DUVALLET, A.SPIE proceedings series. 1999, pp 121-128, isbn 0-8194-3478-7Conference Paper

Fault diagnosis technology based on transistor behavior analysis for physical analysisSANADA, M; YOSHIZAWA, Y.Microelectronics and reliability. 2006, Vol 46, Num 9-11, pp 1575-1580, issn 0026-2714, 6 p.Conference Paper

Dielectrics in SI nano-devices: Roles and challengesQI XIANG; KRIVOKAPIC, Zoran; MASZARA, Witek et al.Proceedings - Electrochemical Society. 2004, pp 86-96, issn 0161-6374, isbn 1-56677-417-9, 11 p.Conference Paper

CMOS four-quadrant multiplier using triode transistors based on regulated cascode structureTSAY, J.-H; SHEN-IUAN LIU; JIANN-JONG CHEN et al.Electronics Letters. 1995, Vol 31, Num 12, pp 962-963, issn 0013-5194Article

Sub-quarter-micrometer CMOS on ultrathin (400 Å) SOIKISTLER, N; PLOEG, E. V; WOO, J et al.IEEE electron device letters. 1992, Vol 13, Num 5, pp 235-237, issn 0741-3106Article

Double edge-triggered D-flip-flops for high-speed CMOS circuitsAFGHAHI, M; YUAN, J.IEEE journal of solid-state circuits. 1991, Vol 26, Num 8, pp 1168-1170, issn 0018-9200Article

Novel electronically-controlled floating resistors using MOS transistors operating in saturationWANG, Z.Electronics Letters. 1991, Vol 27, Num 2, pp 188-189, issn 0013-5194, 2 p.Article

Millesecond annealing for complementary metal-oxide semiconductor source and drain implantsCARTER, J. C; EVANS, A. G. R; TIMANS, P. J et al.Journal of vacuum science and technology. B. Microelectronics processing and phenomena. 1991, Vol 9, Num 4, pp 1944-1949, issn 0734-211XConference Paper

CMOS compatible, self-biased bipolar transistor aimed at detecting maximum temperature in a silicon integrated circuitBAFLEUR, M; BUXO, J; SARRABAYROUSSE, G et al.Electronics Letters. 1988, Vol 24, Num 16, pp 1022-1024, issn 0013-5194Article

Anomalous Dependence of Threshold Voltage Mismatch of Short-Channel TransistorsHOOK, Terence B; JOHNSON, Jeffrey B; SHAH, Jay et al.I.E.E.E. transactions on electron devices. 2011, Vol 58, Num 8, pp 2805-2807, issn 0018-9383, 3 p.Article

Holographic voltage profiling on 75 nm gate architecture CMOS devicesTHESEN, Alexander E; FROST, Bernhard G; JOY, David C et al.Ultramicroscopy. 2003, Vol 94, Num 3-4, pp 277-281, issn 0304-3991, 5 p.Article

Fabrication of diffractive optical elements using the CMOS processDAI, Ching-Liang; CHEN, Hung-Lin; LEE, Chi-Yuan et al.Journal of micromechanics and microengineering (Print). 2002, Vol 12, Num 1, pp 21-25, issn 0960-1317Article

A linearized CMOS transconductor based on bias offset techniqueCZARNIAK, A; SZCZEPAŃSKI, S; JAKUSZ, J et al.Bulletin of the Polish Academy of Sciences. Technical sciences. 1993, Vol 41, Num 1, pp 43-47, issn 0239-7528Article

Floating CMOS resistorWILSON, G; CHAN, P. K.Electronics Letters. 1993, Vol 29, Num 3, pp 306-307, issn 0013-5194Article

Etude des dispositifs MOS de longueur de grille inférieure à 0,1 μm - Vers les limites de l'intégration du CMOS sur silicium = Study of sub-tenth micrometer gate length MOSFETs - Towards the limits of Silicon CMOS integrationCaillat, Christian; Balestra, Francis.1999, 242 p.Thesis

Anwendungsspezifische Simulation integrierter CMOS-Schaltungen = Application specific simulation of integrated CMOS devicesSPALLEK, R. G; SCHLÜSSLER, J.-U.Wissenschaftliche Zeitschrift der Technischen Universität Dresden. 1995, Vol 44, Num 6, pp 14-20, issn 0043-6925Article

Dual collector magnetotransistors with on-chip bias and signal conditioning circuitryCASTAGNETTI, R; AZEREDO LEME, C; BALTES, H et al.Sensors and actuators. A, Physical. 1993, Vol 37-38, pp 698-702, issn 0924-4247Conference Paper

Applications of composite BICMOS transistorsRAMIREZ-ANGULO, J; DEYONG, M; ADAMS, W. J et al.Electronics Letters. 1991, Vol 27, Num 24, pp 2236-2238, issn 0013-5194Article

Characterization of enhanced perimeter leakage in MOS structures following ion implantationSTINSON, M. G; OSBURN, C. M.Journal of the Electrochemical Society. 1990, Vol 137, Num 5, pp 1564-1572, issn 0013-4651Article

Charge-based cCapacitance measurement for bias-dependent capacitanceCHANG, Yao-Wen; CHANG, Hsing-Wen; LU, Tao-Cheng et al.IEEE electron device letters. 2006, Vol 27, Num 5, pp 390-392, issn 0741-3106, 3 p.Article

Module implementation selection and its application to transistor placementHER, T. W; WONG, D. F.IEEE transactions on computer-aided design of integrated circuits and systems. 1997, Vol 16, Num 6, pp 645-651, issn 0278-0070Article