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A write-operation model for the FCAT-II-A SO NS at 15 V alterable nonvolatile memoryHORIUCHI, M.Solid-state electronics. 1984, Vol 27, Num 10, pp 849-854, issn 0038-1101Article

Floating gate memories reliabilityCRISENZA, G; CLEMENTI, C; GHIDINI, G et al.Quality and reliability engineering international. 1992, Vol 8, Num 3, pp 177-187, issn 0748-8017Article

A 35-ns 64K EEPROMJOLLY, R. D; TESCH, R; CAMPBELL, K. J et al.IEEE journal of solid-state circuits. 1985, Vol 20, Num 5, pp 971-978, issn 0018-9200Article

NEW READ-OUT MODE IN LIGHT-SENSITIVE FLOATING GATE MOS MEMORYANDO T; YAMASAKI H.1982; ELECTRON DEVICE LETT.; ISSN 0193-8576; USA; DA. 1982; VOL. 3; NO 4; PP. 83-85; BIBL. 5 REF.Article

A silicon single-electron transistor memory operating at room temperatureGUO, L; LEOBANDUNG, E; CHOU, S. Y et al.Science (Washington, D.C.). 1997, Vol 275, Num 5300, pp 649-651, issn 0036-8075Article

An analytical model for the optimization of source-side injection Flash EEPROM devicesVAN HOUDT, J. F; MAES, H. E.I.E.E.E. transactions on electron devices. 1995, Vol 42, Num 7, pp 1314-1320, issn 0018-9383Article

An analytical model for floating-gate MOSFET including the effects of the overlapping capacitanceMANKU, T; HEASELL, E. L.I.E.E.E. transactions on electron devices. 1992, Vol 39, Num 12, pp 2821-2823, issn 0018-9383Article

AN ELECTRICALLY ALTERABLE NONVOLATILE MEMORY CELL USING A FLOATING-GATE STRUCTUREGUTERMAN DC; RIMAWI IH; CHIU TL et al.1979; I.E.E.E. TRANS. ELECTRON DEVICES; USA; DA. 1979; VOL. 26; NO 4; PP. 576-586; BIBL. 32 REF.Article

HOW A PROM WORKS.SMITH RL.1975; RADIO ELECTRON.; U.S.A.; DA. 1975; VOL. 46; NO 11; PP. 72-119 (4P.)Article

ON THE I-V CHARACTERISTICS OF FLOATING-GATE MOS TRANSISTORSWANG ST.1979; I.E.E.E. TRANS. ELECTRON DEVICES; USA; DA. 1979; VOL. 26; NO 9; PP. 1292-1294; BIBL. 2 REF.Article

ON THE I.V CHARACTERISTICS OF FLOATING-GATE MOS TRANSISTORSTUAN WANG S.1979; I.E.E.E. TRANS. ELECTRON DEVICES; USA; DA. 1979; VOL. 26; NO 9; PP. 1292-1294; BIBL. 2 REF.Article

IMPROVED MOS TRANSDUCER DRIVE CIRCUITBERGER J.1973; I.E.E.E.J. SOLID-STATE CIRCUITS; U.S.A.; DA. 1973; VOL. 8; NO 1; PP. 92-93Serial Issue

A multinanodot floating-gate MOSFET circuit for spiking neuron modelsMORIE, Takashi; MATSUURA, Tomohiro; NAGATA, Makoto et al.IEEE transactions on nanotechnology. 2003, Vol 2, Num 3, pp 158-164, issn 1536-125X, 7 p.Article

Simple method for the determination of the coupling coefficient of floating-gate MOSFETs programmed with Fowler-Nordheim tunnellingREYES-BARRANCA, M. A; MORENO-CADENAS, J. A.IEE proceedings. Circuits, devices and systems. 1999, Vol 146, Num 4, pp 215-217, issn 1350-2409Article

Resolving localized oxide breakthrough during Poly etch of non-volatile floating gates structuresHEALEY, J. T; SIM, V; RUBEL, S et al.SPIE proceedings series. 1998, pp 312-320, isbn 0-8194-2966-XConference Paper

A programmable piecewise linear large-signal CMOS amplifierTHOMSEN, A; BROOKE, M. A.IEEE journal of solid-state circuits. 1993, Vol 28, Num 1, pp 84-89, issn 0018-9200Article

Double doping floating gates improves EPROM yieldsMAKWANA, J; GRULA, B; MONTEILH, D et al.Semiconductor international. 1997, Vol 20, Num 12, pp 125-130, issn 0163-3767, 4 p.Article

A novel approach to controlled programming of tunnel-based floating-gate MOSFET'sLANZONI, M; BRIOZZO, L; RICCO, B et al.IEEE journal of solid-state circuits. 1994, Vol 29, Num 2, pp 147-150, issn 0018-9200Article

A computer-aided scheme of threshold voltage measurement for floating-gate MOS transistorAN SANG HOU.Circuits, systems, and signal processing. 2005, Vol 24, Num 1, pp 83-101, issn 0278-081X, 19 p.Article

History effect characterization in PD-SOI CMOS gatesCASU, M. R; FLATRESSE, P.IEEE International SOI conference. 2002, pp 62-63, isbn 0-7803-7439-8, 2 p.Conference Paper

A non-volatile MOSFET memory device based on mobile protons in SiO2 thin filmsVANHEUSDEN, K; WARREN, W. L; DEVINE, R. A. B et al.Journal of non-crystalline solids. 1999, Vol 254, pp 1-10, issn 0022-3093Conference Paper

A two-dimensional numerical model of a floating-gate EEPROM transistorASQUITH, J; SUNG, C.-L; FAT DUEN HO et al.International journal of electronics. 1998, Vol 85, Num 6, pp 697-712, issn 0020-7217Article

Cast : An electrical stress test to monitor single bit failures in flash-eeprom structuresCAPPELLETTI, P; BEZ, R; CANTARELLI, D et al.Microelectronics and reliability. 1997, Vol 37, Num 3, pp 473-481, issn 0026-2714Article

A new technique for measuring coupling coefficients and 3-D capacitance characterization of floating-gate devicesCHOI, W. L; KIM, D. M.I.E.E.E. transactions on electron devices. 1994, Vol 41, Num 12, pp 2337-2342, issn 0018-9383Article

Etude des transistors à grille flottante et application à la conception d'une mémoire reconfigurable intégrée sur trancheMarron, Dominique; Deneuville, Alain.1989, 220 p.Thesis

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