Impact of high-κ dielectrics on undoped double-gate MOSFET scalingQIANG CHEN; LIHUI WANG; MEINDL, James D et al.IEEE International SOI conference. 2002, pp 115-116, isbn 0-7803-7439-8, 2 p.Conference Paper

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Physical modeling of double-gate transistorZEBREV, G. I.International conference on microelectronics. 2004, isbn 0-7803-8166-1, 2Vol, vol 1, 303-306Conference Paper

Lp/lv ratioed DG-SOI logic with (intrinsically on) symmetric DG-MOSFET loadMITRA, Souvick; SALMAN, Akram; IOANNOU, Dimitris P et al.IEEE International SOI conference. 2002, pp 66-67, isbn 0-7803-7439-8, 2 p.Conference Paper

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Double-gate MOSFET based reconfigurable cellsHASSOUNE, I; O'CONNOR, I.Electronics Letters. 2007, Vol 43, Num 23, pp 1273-1274, issn 0013-5194, 2 p.Article

A self-aligned double-gate MOS transistor technology with individually addressable gatesZHANG, Shengdong; LIN, Xinnan; HUANG, Ru et al.IEEE International SOI conference. 2002, pp 207-208, isbn 0-7803-7439-8, 2 p.Conference Paper

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15-nm-thick Si channel wall vertical double-gate MOSFETMASAHARA, Meishoku; MATSUKAWA, Takashi; ISHII, Ken-Ichi et al.IEDm : international electron devices meeting. 2002, pp 949-951, isbn 0-7803-7462-2, 3 p.Conference Paper

Effects of body doping on threshold voltage and channel potential of symmetric DG MOSFETs with continuous solution from accumulation to strong-inversion regionsFENG LIU; LINING ZHANG; JIAN ZHANG et al.Semiconductor science and technology. 2009, Vol 24, Num 8, issn 0268-1242, 095005.1-095005.8Article

Random dopant fluctuation in limited-width FinFET technologiesCHIANG, Meng-Hsueh; LIN, Jeng-Nan; KIM, Keunwoo et al.I.E.E.E. transactions on electron devices. 2007, Vol 54, Num 8, pp 2055-2060, issn 0018-9383, 6 p.Article

Demonstration and device design consideration of V_th-controllable independent double-gate mosfet (4-terminal XMOS)MASAHARA, M; LIU, Y.-X; SAKAMOTO, K et al.Proceedings - Electrochemical Society. 2005, pp 261-272, issn 0161-6374, isbn 1-56677-461-6, 12 p.Conference Paper

New and accurate method for electrical extraction of silicon film thickness on fully-depleted SOI and double gate transistorsPOIROUX, T; WIDIEZ, J; LOLIVIER, J et al.IEEE international SOI conference. 2004, pp 73-74, isbn 0-7803-8497-0, 1Vol, 2 p.Conference Paper

A simulation-based preview of extremely scaled double-gate CMOS devices and circuitsFOSSUM, Jerry G.International journal of high speed electronics and systems. 2002, Vol 12, Num 2, pp 563-572, 10 p.Conference Paper

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Analysis of dependence of short-channel effects in double-gate MOSFETs on channel thicknessKOBAYASHI, Yusuke; KAKUSHIMA, Kuniyuki; AHMET, Parhat et al.Microelectronics and reliability. 2010, Vol 50, Num 3, pp 332-337, issn 0026-2714, 6 p.Article

4-terminal FinFETs with high threshold voltage controllabilityLIU, Y. X; MASAHARA, M; ISHII, K et al.DRC : Device research conference. 2004, pp 207-208, isbn 0-7803-8284-6, 1Vol, 2 p.Conference Paper

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Characterization of ultra-thin SOI films for double-gate MOSFETsALLIBERT, F; VINET, M; LOLIVIER, J et al.IEEE International SOI conference. 2002, pp 187-188, isbn 0-7803-7439-8, 2 p.Conference Paper

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Analytical unified threshold voltage model of short-channel FinFETs and implementationFASARAKIS, N; TSORMPATZOGLOU, A; TASSIS, D. H et al.Solid-state electronics. 2011, Vol 64, Num 1, pp 34-41, issn 0038-1101, 8 p.Article