Modeling and characterization of gate oxide reliabilityLEE, J. C; IH-CHIN CHEN; CHENMING HU et al.I.E.E.E. transactions on electron devices. 1988, Vol 35, Num 12, pp 2268-2278, issn 0018-9383Article

Structure of the breakdown spot during progressive breakdown of ultra-thin gate oxidesPALUMBO, F; LOMBARDO, S; PEY, K. L et al.IEEE international reliability physics symposium. 2004, pp 583-584, isbn 0-7803-8315-X, 1Vol, 2 p.Conference Paper

Characterization of metal-oxide-semiconductor transistors with very thin gate oxideHUNG, K. K; CHENG, Y. C.Journal of applied physics. 1986, Vol 59, Num 3, pp 816-823, issn 0021-8979Article

Evaluation of phase-edge phase-shifting mask for sub-0.18 μm gate patterns in logic devicesCHA, D.-H; KYE, J.-W; SEONG, N.-G et al.SPIE proceedings series. 1998, pp 46-54, isbn 0-8194-2779-9Conference Paper

Ga_0.47In_0.53As field-effect transistors with a lattice-mismatched reduced leakage current GaAs gateGARBINSKI, P. A; CHEN, C. Y; CHO, A. Y et al.Electronics Letters. 1986, Vol 22, Num 5, pp 236-238, issn 0013-5194Article

The electrical properties of subquarter-micrometer gate-length MOSFET'sHAN-SHENG LEE; CHERYL PUZIO, L.IEEE electron device letters. 1986, Vol 7, Num 11, pp 612-614, issn 0741-3106Article

A novel gate-suppression technique for ESD protectionMENG MIAO; SHURONG DONG; MINGLIANG LI et al.Microelectronics and reliability. 2012, Vol 52, Num 8, pp 1598-1601, issn 0026-2714, 4 p.Conference Paper

Subnanometer-precision metrology for 100nm gate linewidth controlMONAHAN, K. M; MACNAUGHTON, C; NG, W et al.SPIE proceedings series. 1998, pp 110-123, isbn 0-8194-2777-2Conference Paper

Gate technology for 89 GHz vertical doping engineered Si metal-oxide semiconductor field effect transistorJEON, D. Y; TENNANT, D. M; KIM, Y. O et al.Journal of vacuum science & technology. B. Microelectronics and nanometer structures. Processing, measurement and phenomena. 1992, Vol 10, Num 6, pp 2922-2926, issn 1071-1023Conference Paper

Platinum-platinum oxide gate pH ISFETTSUKADA, K; MIYAHARA, Y; MIYAGI, H et al.Japanese journal of applied physics. 1989, Vol 28, Num 12, pp 2450-2453, issn 0021-4922, 1Article

Gate dielectric breakdown : A focus on ESD protectionWEIR, Bonnie E; LEUNG, Che-Choi; SILVERMAN, Paul J et al.IEEE international reliability physics symposium. 2004, pp 399-404, isbn 0-7803-8315-X, 1Vol, 6 p.Conference Paper

0.18 μm optical lithography performances using an alternating DUV phase shift maskTROUILLER, Y; BUFFET, N; MOURIER, T et al.SPIE proceedings series. 1998, pp 25-35, isbn 0-8194-2779-9Conference Paper

A novel method to characterize MOS transistors with mixed gate dielectric technologiesSIERGIEJ, R. R; WHITE, M. H.I.E.E.E. transactions on electron devices. 1992, Vol 39, Num 3, pp 734-737, issn 0018-9383Article

Advanced gate stack, source/drain and channel engineering for Si-based CMOS : naw materials, processes, and equipment (Quebec PQ, 16-18 May 2005)Gusev, Evgeni P; Iwai, Hiroshi; Öztürk, Mehmet C et al.Proceedings - Electrochemical Society. 2005, issn 0161-6374, isbn 1-56677-463-2, XV, 634 p, isbn 1-56677-463-2Conference Proceedings

Line edge roughness: Characterization, modeling and impact on device behaviorCROON, J. A; STORMS, G; WINKELMEIER, S et al.IEDm : international electron devices meeting. 2002, pp 307-310, isbn 0-7803-7462-2, 4 p.Conference Paper

Effect of n⁺―polycrystalline silicon gate rapid thermal annealing on the electrical properties of the gate oxideKOREC, J; STEFFEN, A; MCGINTY, G. K et al.Thin solid films. 1988, Vol 162, pp 21-28, issn 0040-6090Article

Transistor action in novel GaAs/W/GaAs structuresDERKITS, G. E. JR; HARBISON, J. P; LEVKOFF, J et al.Applied physics letters. 1986, Vol 48, Num 18, pp 1220-1222, issn 0003-6951Article

Symmetrical 45nm PMOS on (110) substrate with excellent S/D extension distribution and mobility enhancementHWANG, J. R; HO, J. H; LIN, H. S et al.Symposium on VLSI Technology. sd, pp 90-91, isbn 0-7803-8289-7, 1Vol, 2 p.Conference Paper

The influence of substrate compensation on inter-electrode leakage and back-gating in GaAs MESFETGEORGE, P; KO, P. K; CHENMING HU et al.Solid-state electronics. 1991, Vol 34, Num 3, pp 233-252, issn 0038-1101, 20 p.Article

Applying Litho-Aware Timing Analysis to Hold Time Fixing Reduces Design Cycle Time and Power DissipationHIRABAYASHI, Keisuke; KOBAYASHI, Naohiro; MIZUNO, Hidemichi et al.Proceedings of SPIE, the International Society for Optical Engineering. 2011, Vol 7974, issn 0277-786X, isbn 978-0-8194-8533-5, 797408.1-797408.10Conference Paper

A compact DC model of gate oxide short defectBOUCHAKOUR, R; PORTAL, J. M; GALLIERE, J. M et al.Microelectronic engineering. 2004, Vol 72, Num 1-4, pp 140-148, issn 0167-9317, 9 p.Conference Paper

A reliable and high voltage compatible CMOS I/O bufferCHOW, Hwang-Cherng; CHEN, You-Gang.MWSCAS : Midwest symposium on circuits and systems. 2004, isbn 0-7803-8346-X, 3Vol, Vol III, 451-454Conference Paper

Negative bias temperature instability in triple gate transistorsMAEDA, Shigenobu; CHOI, Jung-A; YANG, Jeong-Hwan et al.IEEE international reliability physics symposium. 2004, pp 8-12, isbn 0-7803-8315-X, 1Vol, 5 p.Conference Paper

Opening a new vista in solid-state science: Tuning electronic properties by gate-induced dopingPANTHÖFER, Martin; JANSEN, Martin.ChemPhysChem (Print). 2002, Vol 3, Num 6, pp 507-509, issn 1439-4235Article

The multiple-gate MOS-JFET transistorBLALOCK, Benjamin J; CRISTOLOVEANU, Sorin; DUFRENE, Brian M et al.International journal of high speed electronics and systems. 2002, Vol 12, Num 2, pp 511-520, 10 p.Conference Paper