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Submicron trenching of semiconductor nanostructuresLEE, K. Y; SMITH, T. P; FORD, C. J. B et al.Applied physics letters. 1989, Vol 55, Num 7, pp 625-627, issn 0003-6951, 3 p.Article

It's quicker under groundLEWIS, A.Concrete (London). 1996, Vol 30, Num 2, issn 0010-5317, p. 25Article

Effects on sidewall profile of Si etched in BCI3/Cl2 chemistryJER-SHEN MAA; GOSSENBERGER, H; HAMMER, L et al.Journal of vacuum science and technology. B. Microelectronics processing and phenomena. 1990, Vol 8, Num 4, pp 581-585, issn 0734-211X, 5 p.Article

Nearly bird's beak-free local oxidation technology for controlled dielectic formation in deep silicon trenchesSHENAI, K.Electronics Letters. 1991, Vol 27, Num 8, pp 637-639, issn 0013-5194, 3 p.Article

Lifetime of thin oxide and oxide-nitride-oxide dielectrics within trench capacitors for DRAM'sHIERGEIST, P; SPITZER, A; RÖHL, S et al.I.E.E.E. transactions on electron devices. 1989, Vol 36, Num 5, pp 913-919, issn 0018-9383, 7 p.Article

A novel 248-nm wet-developable BARC for trench applicationsNEEF, Charles J; THOMAS, Deborah.Proceedings of SPIE, the International Society for Optical Engineering. 2007, pp 65192Z.1-65192Z.8, issn 0277-786X, isbn 978-0-8194-6638-9Conference Paper

Experimental study and simulations on two different avalanche modes in trench power MOSFETsPAWEL, I; SIEMIENIEC, R; RÖSCH, M et al.IET circuits, devices & systems (Print). 2007, Vol 1, Num 5, pp 341-346, issn 1751-858X, 6 p.Conference Paper

Micro/macrocavity method applied to the study of the step coverage formation mechanism of SiO2 films by LPCVDWATANABE, K; KOMIYAMA, H.Journal of the Electrochemical Society. 1990, Vol 137, Num 4, pp 1222-1227, issn 0013-4651, 6 p.Article

Doping of trench capacitors by rapid thermal diffusionZAGOZDZON-WOSIK, W; WOLFE, J. C; TENG, C. W et al.IEEE electron device letters. 1991, Vol 12, Num 6, pp 264-266, issn 0741-3106, 3 p.Article

Electron mobilities in MOS channels formed along anisotropically dry etched < 110 < silicon trench sidewallsSHENAI, K.Electronics Letters. 1991, Vol 27, Num 9, pp 715-717, issn 0013-5194, 3 p.Article

Using trenches to reduce tunnelling vibrationsRAHMAN, M. E; ORR, T. L. L.Proceedings of the Institution of Civil Engineers - Geotechnical engineering. 2008, Vol 161, Num 5, pp 227-233, issn 1353-2618, 7 p.Article

A multi trench analog+logic protection (M-TRAP) for substrate crosstalk prevention in a 0.25μm smart power platform with 100V high-side capabilityPARTHASARATHY, V; KHEMKA, V; ZHU, R et al.International Symposium on Power Semiconductor Devices & ICs. 2004, pp 427-430, isbn 4-88686-060-5, 4 p.Conference Paper

On-chip isolation in wafer-level chip-scale packages: Substrate thinning and circuit partitioning by trenchesSINAGA, S. M; POLYAKOV, A; BARTEK, M et al.SPIE proceedings series. 2003, pp 768-773, isbn 0-8194-5189-4, 6 p.Conference Paper

New trencher makes Troll inaugurationOffshore technology. 2000, Vol 8, Num 4, pp 27-30, 2 p.Article

MOS controlled diodes : a new power diodeQIN HUANG; AMARATUNGA, G. A. J.Solid-state electronics. 1995, Vol 38, Num 5, pp 977-980, issn 0038-1101Article

Challenges for quality 15nm groove patterning with ZEP520A for a master fabrication for track pitch 50nm full-surface DTR-MediaIYAMA, Hiromasa; HAMAMOTO, Kazuhiro; KISHIMOTO, Shuji et al.Proceedings of SPIE, the International Society for Optical Engineering. 2010, Vol 7748, issn 0277-786X, isbn 0-8194-8238-2 978-0-8194-8238-9, 1Vol, 77481Z.1-77481Z.5Conference Paper

Micro projection lithography using microlens on a maskJI, Chang-Hyeon; HERRAULT, Florian; ALLEN, Mark G et al.Journal of micromechanics and microengineering (Print). 2009, Vol 19, Num 12, issn 0960-1317, 127003.1-127003.6Article

Fabrication and characterization of gated carbon nanotube emitters in a trench structureLIAO, Y. F; SHE, J. C; HE, H et al.International Vacuum Nanoelectronics Conference. 2004, pp 66-67, isbn 0-7803-8397-4, 1Vol, 2 p.Conference Paper

Silicon trench undercutting caused by the preferential plasma etching of surface-implanted regionsKRISHNA SHENAI.I.E.E.E. transactions on electron devices. 1992, Vol 39, Num 3, pp 737-738, issn 0018-9383Article

Silicide/high-k dielectric structures for nanotransistor gatesHORIN, I. A; KRIVOSPITSKY, A. D; ORLIKOVSKY, A. A et al.Proceedings of SPIE, the International Society for Optical Engineering. 2006, pp 62600G.1-62600G.8, issn 0277-786X, isbn 0-8194-6325-6, 1VolConference Paper

On increasing the accuracy of simulations of deposition and etching processes using radiosity and the level set methodHEITZINGER, Clemens; FUGGER, Josef; SELBERHERR, Siegfried et al.ESSCIRC 2002 : European solid-state circuits conferenceEuropean solid-state device research conference. 2002, pp 347-350, isbn 88-900847-8-2, 4 p.Conference Paper

Strategies and test structures for improving isolation between circuit blocksSZMYD, David; GAMBUS, Laurent; WILBANKS, William et al.2002 international conference on microelectronic test structures. 2002, pp 89-93, isbn 0-7803-7464-9, 5 p.Conference Paper

A high accuracy resonant pressure sensor by fusion bonding and trench etchingWELHAM, C. J; GREENWOOD, J; BERTIOLI, M. M et al.Sensors and actuators. A, Physical. 1999, Vol 76, Num 1-3, pp 298-304, issn 0924-4247Conference Paper

Stresses in silicon substrates near isolation trenchesCHIDAMBARRAO, D; PENG, J. P; SRINIVASAN, G. R et al.Journal of applied physics. 1991, Vol 70, Num 9, pp 4816-4822, issn 0021-8979Article

Three-additive model of superfilling of copperYANG CAO; TAEPHAISITPHONGSE, Premratn; CHALUPA, Radek et al.Journal of the Electrochemical Society. 2001, Vol 148, Num 7, pp C466-C472, issn 0013-4651Article

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