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Results 1 to 25 of 291

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Selected papers from the ULIS 2011 ConferenceFERAIN, Isabelle; FIEGNA, Claudio.Solid-state electronics. 2012, Vol 71, issn 0038-1101, 115 p.Conference Proceedings

Papers Selected from the Ultimate Integration on Silicon Conference 2009, ULIS 2009LEMME, Max; MANTL, Siegfried.Solid-state electronics. 2009, Vol 53, Num 12, issn 0038-1101, 126 p.Serial Issue

New trends in plasma etching for Ultra Large Scale Integration TechnologyJOUBERT, O.Microelectronic engineering. 1998, Vol 41-42, pp 17-24, issn 0167-9317Conference Paper

2005 ULIS Conference. Selected papersSANGIORGI, Enrico; FIEGNA, Claudio.Solid-state electronics. 2006, Vol 50, Num 1, issn 0038-1101, 104 p.Conference Proceedings

Characterization and metrology for ULSI technologySEILER, David G.IEEE transactions on semiconductor manufacturing. 2006, Vol 19, Num 4, pp 372-403, issn 0894-6507, 31 p.Conference Paper

Differential silicide thickness for ULSI scalingTAYLOR, William J; SMITH, James; NGUYEN, Jen-Yee et al.Proceedings - Electrochemical Society. 2003, pp 278-287, issn 0161-6374, isbn 1-56677-376-8, 10 p.Conference Paper

Carbon nanotube technologies for future ULSI via interconnectsAWANO, Yuji.SPIE proceedings series. 2005, pp 37-44, isbn 0-8194-5706-X, 8 p.Conference Paper

The double jet ionizer for ULSI manufacturing processes : Special section on issues related to semiconductor manufacturing at technology nodes below 70 nmIMAZONO, Hiroyuki; TERASHIGE, Takashi; OKANO, Kazuo et al.IEEE transactions on semiconductor manufacturing. 2002, Vol 15, Num 2, pp 189-193, issn 0894-6507Article

Improvements in both thermal stability of Ni-silicide and electrical reliability of gate oxides using a stacked polysilicon gate structureJAM WEM LEE; LIN, Shen-Xiang; LEI, Tan-Fu et al.Journal of the Electrochemical Society. 2001, Vol 148, Num 9, pp G530-G533, issn 0013-4651Article

Epitaxial silicide interfaces in microelectronicsTUNG, R. T; OHMI, S.Thin solid films. 2000, Vol 369, Num 1-2, pp 233-239, issn 0040-6090Conference Paper

Compact quasi-analytic equations for estimating the temperature distribution of ULSI interconnectionsXIAO, X; YOU, X; RUAN, G et al.Microelectronic engineering. 2002, Vol 60, Num 3-4, pp 415-428, issn 0167-9317Article

Special Issue with Papers Selected from the Ultimate Integration on Silicon Conference, Ulis 2008SELMI, Luca; ESSENI, David; PALESTRI, Pierpaolo et al.Solid-state electronics. 2009, Vol 53, Num 4, issn 0038-1101, 68 p.Serial Issue

Thin film transistors in ULSI -status and futureYUE KUO.Proceedings - Electrochemical Society. 2003, pp 322-329, issn 0161-6374, isbn 1-56677-376-8, 8 p.Conference Paper

Novel SOI-like structures for improved thermal dissipationOSHIMA, K; CRISTOLOVEANU, S; GUILLAUMOT, B et al.IEEE International SOI conference. 2002, pp 95-96, isbn 0-7803-7439-8, 2 p.Conference Paper

Modelling and simulation for dielectric constant of aerogelXIA XIAO; STREITER, Reinhard; GANG RUAN et al.Microelectronic engineering. 2000, Vol 54, Num 3-4, pp 295-301, issn 0167-9317Article

A new concept of p-(n-)/p-(n-) thin-film epitaxial silicon wafers for MOS ULSI's that ensures excellent gate oxide integritySHIMIZU, H; SUGINO, Y; SUZUKI, N et al.IEEE transactions on semiconductor manufacturing. 1998, Vol 11, Num 2, pp 239-245, issn 0894-6507Conference Paper

Simplified monitoring technique for line-short defects that provides high sensitivity and high throughput : Technologies supporting semiconductor scientific manufacturing : Process monitoring, testing, failure analysis and reliabilityKIKUCHI, Hiroaki; KODAMA, Noriyuki; NISHIO, Naoharu et al.NEC research & development. 2000, Vol 41, Num 4, pp 332-335, issn 0547-051XArticle

Mainstreaming SOI CMOS technologySHAHIDI, G. G.SPIE proceedings series. 1999, pp 15-21, isbn 0-8194-3480-9Conference Paper

Current status of failure analysis for ULSIsNAKAJIMA, S; UEKI, T; SHIONOYA, Y et al.Microelectronics and reliability. 1998, Vol 38, Num 9, pp 1369-1377, issn 0026-2714Article

Tool commonality analysis for yield enhancementKONG, George.ASMC proceedings. 2002, pp 202-205, issn 1078-8743, isbn 0-7803-7158-5, 4 p.Conference Paper

Study on the deposition profile characteristics in the micron-scale trench using direct simulation Monte Carlo methodIKEGAWA, M; KOBAYASHI, J; MARUKO, M et al.Journal of fluids engineering. 1998, Vol 120, Num 2, pp 296-302, issn 0098-2202Article

Topography simulation for interconnect depositionREY, J. C; LI, J; BOKSHA, V et al.Solid state technology. 1998, Vol 41, Num 2, pp 77-82, issn 0038-111X, 4 p.Article

High-performance and damage-free neutral-beam etching processes using negative ions in pulse-time-modulated plasmaSAMUKAWA, Seiji.Applied surface science. 2007, Vol 253, Num 16, pp 6681-6689, issn 0169-4332, 9 p.Article

Unveiling the electromigration physics of ULSI interconnects through statisticsCHER MING TAN; RAGHAVAN, Nagarajan.Semiconductor science and technology. 2007, Vol 22, Num 8, pp 941-946, issn 0268-1242, 6 p.Article

An efficient low-degree RMST algorithm for VLSI/ULSI physical designYIN WANG; XIANLONG HONG; TONG JING et al.Lecture notes in computer science. 2004, pp 442-452, issn 0302-9743, isbn 3-540-23095-5, 11 p.Conference Paper

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