A conventional 45nm CMOS node low-cost platform for general purpose and low power applicationsBOEUF, F; ARNAUD, F; PAIN, L et al.International Electron Devices Meeting. 2004, pp 425-428, isbn 0-7803-8684-1, 1Vol, 4 p.Conference Paper

Gate stack optimization for 65nm CMOS Low Power and High Performance platformDURIEZ, B; TAVEL, B; PALLA, R et al.International Electron Devices Meeting. 2004, pp 847-850, isbn 0-7803-8684-1, 1Vol, 4 p.Conference Paper

New concept of high-k integration in MOSFET's by a deposition through contact holesHARRISON, S; CORONEL, P; WACQUANT, F et al.Microelectronic engineering. 2004, Vol 72, Num 1-4, pp 321-325, issn 0167-9317, 5 p.Conference Paper

Optimized nickel silicide process formation for high performance sub-65nm CMOS nodesFROMENT, B; CARRON, V; MORAND, Y et al.Proceedings - Electrochemical Society. 2004, pp 191-201, issn 0161-6374, isbn 1-56677-406-3, 11 p.Conference Paper

Work function tuning through dopant scanning and related effects in Ni fully silicided gate for sub-45nm nodes CMOSAIME, D; FROMENT, B; LAVIRON, C et al.International Electron Devices Meeting. 2004, pp 87-90, isbn 0-7803-8684-1, 1Vol, 4 p.Conference Paper

New metal gate architecture achieved by chemical vapor deposition for a complete tunnel fillREGNIER, C; WACQUANT, F; LEVERD, F et al.Proceedings - Electrochemical Society. 2003, pp 391-396, issn 0161-6374, isbn 1-56677-396-2, 6 p.Conference Paper

Low cost 65nm CMOS platform for low power & general purpose applicationsARNAUD, F; DURIEZ, B; REYNARD, J. P et al.Symposium on VLSI Technology. sd, pp 10-11, isbn 0-7803-8289-7, 1Vol, 2 p.Conference Paper

Design of experiment on the CO salicide process: Impact of thickness and anneals on main CMOS parametersWACQUANT, F; REGNIER, C; BASSO, M.-T et al.Proceedings - Electrochemical Society. 2003, pp 191-196, issn 0161-6374, isbn 1-56677-396-2, 6 p.Conference Paper

Spike anneal optimization for digital and analogue high performance 0.13 μm CMOS platformJOSSE, E; ARNAUD, F; WACQUANT, F et al.ESSCIRC 2002 : European solid-state circuits conferenceEuropean solid-state device research conference. 2002, pp 207-210, isbn 88-900847-8-2, 4 p.Conference Paper

Ultra-low cost and high performance 65nm CMOS device fabricated with plasma dopingLALLEMENT, F; DURIEZ, B; GODET, L et al.Symposium on VLSI Technology. sd, pp 178-179, isbn 0-7803-8289-7, 1Vol, 2 p.Conference Paper