A Discussion on SRAM Circuit Design Trend in Deeper Nanometer-Scale TechnologiesYAMAUCHI, Hiroyuki.IEEE transactions on very large scale integration (VLSI) systems. 2010, Vol 18, Num 5, pp 763-774, issn 1063-8210, 12 p.Article

A 1R/1W SRAM cell design to keep cell current and area saving against simultaneous read/write disturbed accesses : Low-power, high-speed LSIs and related technologiesYAMAUCHI, Hiroyuki; SUZUKI, Toshikazu; YAMAGAMI, Yoshinobu et al.IEICE transactions on electronics. 2007, Vol 90, Num 4, pp 749-757, issn 0916-8524, 9 p.Article

Intergranular environmentally assisted cracking of Alloy 182 weld metal in simulated normal water chemistry of boiling water reactorQUNJIA PENG; SHOJI, Tetsuo; YAMAUCHI, Hiroyuki et al.Corrosion science. 2007, Vol 49, Num 6, pp 2767-2780, issn 0010-938X, 14 p.Article

Eosinophilic Granuloma of the Middle EarUEKI, Shigeharu; YAMAUCHI, Hiroyuki; TAKEDA, Masahide et al.Journal of rheumatology. 2011, Vol 38, Num 9, pp 2005-2006, issn 0315-162X, 2 p.Article

A Stable 2-Port SRAM Cell Design Against Simultaneously Read/Write-Disturbed AccessesSUZUKI, Toshikazu; YAMAUCHI, Hiroyuki; YAMAGAMI, Yoshinobu et al.IEEE journal of solid-state circuits. 2008, Vol 43, Num 9, pp 2109-2119, issn 0018-9200, 11 p.Article

A 322 MHz random-cycle embedded DRAM with high-accuracy sensing and tuningIIDA, Masahisa; KURODA, Naoki; GYOHTEN, Takayuki et al.IEEE journal of solid-state circuits. 2005, Vol 40, Num 11, pp 2296-2304, issn 0018-9200, 9 p.Article

A PND (PMOS-NMOS-depletion MOS) type single poly gate non-volatile memory cell design with a differential cell architecture in a pure CMOS logic process for a system LSIYAMAMOTO, Yasue; SHIRAHAMA, Masanori; KAWASAKI, Toshiaki et al.IEICE transactions on electronics. 2007, Vol 90, Num 5, pp 1129-1137, issn 0916-8524, 9 p.Article

A 400-MHz random-cycle dual-port interleaved dram (D²RAM) with standard CMOS processSHIRAHAMA, Masanori; AGATA, Yasuhiro; HONDA, Shinji et al.IEEE journal of solid-state circuits. 2005, Vol 40, Num 5, pp 1200-1207, issn 0018-9200, 8 p.Article

An Over-1-Gb/s Transceiver Core for Integration Into Large System-on-Chips for Consumer ElectronicsYOSHIKAWA, Takefumi; HIRATA, Takashi; EBUCHI, Tsuyoshi et al.IEEE transactions on very large scale integration (VLSI) systems. 2008, Vol 16, Num 9, pp 1187-1198, issn 1063-8210, 12 p.Article

Influence of adsorption on the gas permeation performances in the mesoporous alumina ceramic membraneLEE, Hong-Joo; YAMAUCHI, Hiroyuki; SUDA, Hiroyuki et al.Separation and purification technology. 2006, Vol 49, Num 1, pp 49-55, issn 1383-5866, 7 p.Article

0.3-1.5 V embedded SRAM core with write-replica circuit using asymmetrical memory cell and source-level-adjusted direct-sense-amplifier : Lower-power LSI and lower-power IPSUZUKI, Toshikazu; YAMAGAMI, Yoshinobu; HATANAKA, Ichiro et al.IEICE transactions on electronics. 2005, Vol 88, Num 4, pp 630-638, issn 0916-8524, 9 p.Article

A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-V_TH Read-Port, and Offset Cell VDD Biasing TechniquesCHANG, Meng-Fan; CHEN, Ming-Pin; YAMAUCHI, Hiroyuki et al.IEEE journal of solid-state circuits. 2013, Vol 48, Num 10, pp 2558-2569, issn 0018-9200, 12 p.Article

Low-Voltage Embedded NAND-ROM Macros Using Data-Aware Sensing Reference Scheme for VDDmin, Speed and Power ImprovementYANG, Shu-Meng; CHANG, Meng-Fan; CHIANG, Chi-Chuang et al.IEEE journal of solid-state circuits. 2013, Vol 48, Num 2, pp 611-623, issn 0018-9200, 13 p.Article

A Large σV_TH/VDD Tolerant Zigzag 8T SRAM With Area-Efficient Decoupled Differential Sensing and Fast Write-Back SchemeWU, Jui-Jen; CHEN, Yen-Huei; CHANG, Meng-Fan et al.IEEE journal of solid-state circuits. 2011, Vol 46, Num 4, pp 815-827, issn 0018-9200, 13 p.Conference Paper

Fibrocytes are involved in the pathogenesis of human chronic kidney diseaseSAKAI, Norihiko; FURUICHI, Kengo; TAKEDA, Shin-Ichi et al.Human pathology. 2010, Vol 41, Num 5, pp 672-678, issn 0046-8177, 7 p.Article

A 0.6 V Dual-Rail Compiler SRAM Design on 45 nm CMOS Technology With Adaptive SRAM Power for Lower VDD_min VLSIsYEN HUEI CHEN; CHAN, Gary; SHAO YU CHOU et al.IEEE journal of solid-state circuits. 2009, Vol 44, Num 4, pp 1209-1215, issn 0018-9200, 7 p.Conference Paper

Hydrogen production by high temperature electrolysis with nuclear reactorFUJIWARA, Seiji; KASAI, Shigeo; HOASHI, Eiji et al.Progress in nuclear energy (New series). 2008, Vol 50, Num 2-6, pp 422-426, issn 0149-1970, 5 p.Conference Paper

A method and language for constructing multiagent systemsYAMAUCHI, Hiroyuki; OHSUGA, Setsuo.Lecture notes in computer science. 2000, pp 619-628, issn 0302-9743, isbn 3-540-41094-5Conference Paper