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Performance Study of a Schottky Barrier Double-Gate MOSFET Using a Two-Dimensional Analytical ModelSCHWARZ, Mike; HOLTIJ, Thomas; KLOES, Alexander et al.I.E.E.E. transactions on electron devices. 2013, Vol 60, Num 2, pp 884-886, issn 0018-9383, 3 p.Article

N-Port T-Networks and Topologically Symmetric Circuit TheoryRAUTIO, James C.IEEE transactions on microwave theory and techniques. 2010, Vol 58, Num 4, pp 705-709, issn 0018-9480, 5 p.Article

Source-drain partitioning in MOSFETROY, Ananda S; ENZ, Christian C; SALLESE, Jean-Michel et al.I.E.E.E. transactions on electron devices. 2007, Vol 54, Num 6, pp 1384-1393, issn 0018-9383, 10 p.Article

Accurate Compact Modeling for Sub-20-nm NAND Flash Cell Array Simulation Using the PSP ModelJEON, Jongwook; IL HAN PARK; KANG, Myounggon et al.I.E.E.E. transactions on electron devices. 2012, Vol 59, Num 12, pp 3503-3509, issn 0018-9383, 7 p.Article

Implementation of Tunneling Phenomena in a CNTFET Compact ModelFREGONESE, Sébastien; MANEUX, Cristell; ZIMMER, Thomas et al.I.E.E.E. transactions on electron devices. 2009, Vol 56, Num 10, pp 2224-2231, issn 0018-9383, 8 p.Article

Computationally Efficient Physics-Based Compact CNTFET Model for Circuit DesignFREGONESE, Sébastien; CAZIN D'HONINCTHUN, Hugues; GOGUET, Johnny et al.I.E.E.E. transactions on electron devices. 2008, Vol 55, Num 6, pp 1317-1327, issn 0018-9383, 11 p.Article

Generic Carrier-Based Core Model for Undoped Four-Terminal Double-Gate MOSFETs Valid for Symmetric, Asymmetric, and Independent-Gate-Operation ModesFENG LIU; JIN HE; YUE FU et al.I.E.E.E. transactions on electron devices. 2008, Vol 55, Num 3, pp 816-826, issn 0018-9383, 11 p.Article

Physics-based compact model of nanoscale MOSFETs- : Part II: Effects of degeneracy on transportMUGNAINI, Giorgio; LANNACCONE, Giuseppe.I.E.E.E. transactions on electron devices. 2005, Vol 52, Num 8, pp 1802-1806, issn 0018-9383, 5 p.Article

Electrical Modeling of Stochastic Spin Transfer Torque Writing in Magnetic Tunnel Junctions for Memory and Logic ApplicationsYUE ZHANG; WEISHENG ZHAO; PRENAT, Guillaume et al.IEEE transactions on magnetics. 2013, Vol 49, Num 7, pp 4375-4378, issn 0018-9464, 4 p.Conference Paper

Piecewise Linearization Technique for Compact Charge Modeling of Independent DG MOSFETJANDHYALA, Srivatsava; ABRAHAM, Aby; ANGHEL, Costin et al.I.E.E.E. transactions on electron devices. 2012, Vol 59, Num 7, pp 1974-1979, issn 0018-9383, 6 p.Article

An Efficient Robust Algorithm for the Surface-Potential Calculation of Independent DG MOSFETJANDHYALA, Srivatsava; MAHAPATRA, Santanu.I.E.E.E. transactions on electron devices. 2011, Vol 58, Num 6, pp 1663-1671, issn 0018-9383, 9 p.Article

Large-Signal Model for Independent DG MOSFETPANKAJ KUMAR THAKUR; MAHAPATRA, Santanu.I.E.E.E. transactions on electron devices. 2011, Vol 58, Num 1, pp 46-52, issn 0018-9383, 7 p.Article

A physics-based analytic solution to the MOSFET surface potential from accumulation to strong-inversion regionJIN HE; MANSUN CHAN; XING ZHANG et al.I.E.E.E. transactions on electron devices. 2006, Vol 53, Num 9, pp 2008-2016, issn 0018-9383, 9 p.Article

A unified compact model of electrical and thermal 3-D spreading resistance between eccentric rectangular and circular contactsKARMALKAR, Shreepad; VISHNU MOHAN, P; PRESENNA KUMAR, B et al.IEEE electron device letters. 2005, Vol 26, Num 12, pp 909-912, issn 0741-3106, 4 p.Article

Realization of multiple valued logic and memory by hybrid SETMOS architectureMAHAPATRA, Santanu; IONESCU, Adrian Mihai.IEEE transactions on nanotechnology. 2005, Vol 4, Num 6, pp 705-714, issn 1536-125X, 10 p.Article

A Compact Model for Organic Field-Effect Transistors With Improved Output Asymptotic BehaviorsHYUN KIM, Chang; CASTRO-CARRANZA, Alejandra; ESTRADA, Magali et al.I.E.E.E. transactions on electron devices. 2013, Vol 60, Num 3, pp 1136-1141, issn 0018-9383, 6 p.Article

A Simple Charge Model for Symmetric Double-Gate MOSFETs Adapted to Gate-Oxide-Thickness AsymmetryJANDHYALA, Srivatsava; KASHYAP, Rutwick; ANGHEL, Costin et al.I.E.E.E. transactions on electron devices. 2012, Vol 59, Num 4, pp 1002-1007, issn 0018-9383, 6 p.Article

Compact Modeling of a Generic Double-Gate MOSFET With Gate―S/D Underlap for Subthreshold OperationVADDI, Ramesh; AGARWAL, R. P; DASGUPTA, S et al.I.E.E.E. transactions on electron devices. 2012, Vol 59, Num 10, pp 2846-2849, issn 0018-9383, 4 p.Article

Improvements in Efficiency of Surface Potential Computation for Independent DG MOSFETABRAHAM, Aby; JANDHYALA, Srivatsava; MAHAPATRA, Santanu et al.I.E.E.E. transactions on electron devices. 2012, Vol 59, Num 4, pp 1199-1202, issn 0018-9383, 4 p.Article

A Charge-Based OTFT Model for Circuit SimulationTORRICELLI, Fabrizio; KOVACS-VAJNA, Zsolt M; COLALONGO, Luigi et al.I.E.E.E. transactions on electron devices. 2009, Vol 56, Num 1, pp 20-30, issn 0018-9383, 11 p.Article

Compact models of spreading resistances for electrical/thermal design of devices and ICsKARMALKAR, Shreepad; VISHNU MOHAN, P; NAIR, Hari P et al.I.E.E.E. transactions on electron devices. 2007, Vol 54, Num 7, pp 1734-1743, issn 0018-9383, 10 p.Article

Noise modeling methodologies in the presence of mobility degradation and their equivalenceROY, Ananda S; ENZ, Christian C; SALLESE, Jean-Michel et al.I.E.E.E. transactions on electron devices. 2006, Vol 53, Num 2, pp 348-355, issn 0018-9383, 8 p.Article

Analytic solution of the channel potential in undoped symmetric dual-gate MOSFETsORTIZ-CONDE, Adelmo; GARCIA-SANCHEZ, Francisco J; MALOBABIC, Slavica et al.I.E.E.E. transactions on electron devices. 2005, Vol 52, Num 7, pp 1669-1672, issn 0018-9383, 4 p.Article

An improved junction capacitance model for junction field-effect transistorsHAO DING; LIOU, Juin J; CIRBA, Claude R et al.Solid-state electronics. 2006, Vol 50, Num 7-8, pp 1395-1399, issn 0038-1101, 5 p.Article

Benchmark tests on surface potential based charge-sheet modelsJIN HE; XING ZHANG; GANGGANG ZHANG et al.Solid-state electronics. 2006, Vol 50, Num 2, pp 263-267, issn 0038-1101, 5 p.Article

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