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A Low Power High-Speed 8-Bit Pipelining CLA Design Using Dual-Threshold Voltage Domino LogicWANG, Chua-Chin; HUANG, Chi-Chun; LEE, Ching-Li et al.IEEE transactions on very large scale integration (VLSI) systems. 2008, Vol 16, Num 5, pp 594-598, issn 1063-8210, 5 p.Article

Noise constrained transistor sizing and power optimization for dual V_t domino logicJUNG, Seong-Ook; KIM, Ki-Wook; KANG, Sung-Mo et al.IEEE transactions on very large scale integration (VLSI) systems. 2002, Vol 10, Num 5, pp 532-541, issn 1063-8210, 10 p.Article

Current-Comparison-Based Domino: New Low-Leakage High-Speed Domino Circuit for Wide Fan-In GatesPEIRAVI, Ali; ASYAEI, Mohammad.IEEE transactions on very large scale integration (VLSI) systems. 2013, Vol 21, Num 5, pp 937-943, issn 1063-8210, 7 p.Article

Domino CMOS SCD/SFS 2-out-of-3 and 1-out-of-3 code checkersHANIOTAKIS, Th; TSIATOUHAS, Y; EFSTATHIOU, C et al.International journal of electronics. 2003, Vol 90, Num 2, pp 145-158, issn 0020-7217, 14 p.Article

Low power wide gates for modern power efficient processorsASYAEI, Mohammad; PEIRAVI, Ali.Integration (Amsterdam). 2014, Vol 47, Num 2, pp 272-283, issn 0167-9260, 12 p.Article

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Robust low leakage controlled keeper by current-comparison domino for wide fan-in gatesPEIRAVI, Ali; ASYAEI, Mohammad.Integration (Amsterdam). 2012, Vol 45, Num 1, pp 22-32, issn 0167-9260, 11 p.Article

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Sleep switch dual threshold voltage domino logic with reduced subthreshold and gate oxide leakage currentZHIYU LIU; KURSUN, Volkan.Microelectronics journal. 2006, Vol 37, Num 8, pp 812-820, issn 0959-8324, 9 p.Article