A High-Level Simulink-Based Tool for FPAA ConfigurationSCHLOTTMANN, Craig R; PETRE, Csaba; HASLER, Paul E et al.IEEE transactions on very large scale integration (VLSI) systems. 2012, Vol 20, Num 1, pp 10-18, issn 1063-8210, 9 p.Article

A Switched Gain Resonant Controller to Minimize Image Artifacts in Intermittent Contact Mode Atomic Force MicroscopyFAIRBAIRN, Matthew W; REZA MOHEIMANI, S. O.IEEE transactions on nanotechnology. 2012, Vol 11, Num 6, pp 1126-1134, issn 1536-125X, 9 p.Article

A Translinear, Log-Domain FPAA on Standard CMOS TechnologyFERNANDEZ, Daniel; MARTINEZ-ALVARADO, Luis; MADRENAS, Jordi et al.IEEE journal of solid-state circuits. 2012, Vol 47, Num 2, pp 490-503, issn 0018-9200, 14 p.Article

Placement for large-scale floating-gate field-programable analog arraysBASKAYA, Faik; REDDY, Sasank; SUNG KYU LIM et al.IEEE transactions on very large scale integration (VLSI) systems. 2006, Vol 14, Num 8, pp 906-910, issn 1063-8210, 5 p.Article

A Field-Programmable Analog Array of 55 Digitally Tunable OTAs in a Hexagonal LatticeBECKER, Joachim; HENRICI, Fabian; TRENDELENBURG, Stanis et al.IEEE journal of solid-state circuits. 2008, Vol 43, Num 12, pp 2759-2768, issn 0018-9200, 10 p.Conference Paper

A Digitally Enhanced Dynamically Reconfigurable Analog Platform for Low-Power Signal ProcessingSCHLOTTMANN, Craig R; SHAPERO, Samuel; NEASE, Stephen et al.IEEE journal of solid-state circuits. 2012, Vol 47, Num 9, pp 2174-2184, issn 0018-9200, 11 p.Article

Floating Gate-Based Field Programmable Mixed-Signal ArrayWUNDERLICH, Richard B; ADIL, Farhan; HASLER, Paul et al.IEEE transactions on very large scale integration (VLSI) systems. 2013, Vol 21, Num 8, pp 1496-1505, issn 1063-8210, 10 p.Article