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Low Power Magnetic Full-Adder Based on Spin Transfer Torque MRAMERYA DENG; YUE ZHANG; KLEIN, Jacques-Olivier et al.IEEE transactions on magnetics. 2013, Vol 49, Num 9, pp 4982-4987, issn 0018-9464, 6 p.Article
High Speed, High Stability and Low Power Sensing Amplifier for MTJ/CMOS Hybrid Logic CircuitsWEISHENG ZHAO; CHAPPERT, Claude; JAVERLIAC, Virgile et al.IEEE transactions on magnetics. 2009, Vol 45, Num 10, pp 3784-3787, issn 0018-9464, 4 p.Conference Paper
A 100 μW 128 × 64 Pixels Contrast-Based Asynchronous Binary Vision Sensor for Sensor Networks ApplicationsGOTTARDI, Massimo; MASSARI, Nicola; ARSALAN JAWED, Syed et al.IEEE journal of solid-state circuits. 2009, Vol 44, Num 5, pp 1582-1592, issn 0018-9200, 11 p.Article
A new low power test pattern generator for BIST architectureKIM, Kicheol; SONG, Dongsub; KIM, Incheol et al.IEICE transactions on electronics. 2005, Vol 88, Num 10, pp 2037-2038, issn 0916-8524, 2 p.Article
Minimum Energy per Bit in Broadcast and Interference Channels With Correlated InformationHØST-MADSEN, Anders.IEEE transactions on information theory. 2013, Vol 59, Num 6, pp 3796-3810, issn 0018-9448, 15 p.Article
Domain Wall Shift Register-Based Reconfigurable LogicWEISHENG ZHAO; RAVELOSONA, Dafine; KLEIN, Jacques-Olivier et al.IEEE transactions on magnetics. 2011, Vol 47, Num 10, pp 2966-2969, issn 0018-9464, 4 p.Conference Paper
Self-Enabled Error-Free Switching Circuit for Spin Transfer Torque MRAM and LogicLAKYS, Yahya; WEI SHENG ZHAO; DEVOLDER, Thibaut et al.IEEE transactions on magnetics. 2012, Vol 48, Num 9, pp 2403-2406, issn 0018-9464, 4 p.Article
A High-Reliability, Low-Power Magnetic Full AdderYI GANG; WEISHENG ZHAO; KLEIN, Jacques-Olivier et al.IEEE transactions on magnetics. 2011, Vol 47, Num 11, pp 4611-4616, issn 0018-9464, 6 p.Article
ISLPED'04 (proceedings of the 2004 International Symposium on Low Power Electronics and Design)International Symposium on Low Power Electronics and Design. 2004, isbn 1-58113-929-2, 1Vol, XIII-400 p, isbn 1-58113-929-2Conference Proceedings
ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)MARCULESCU, Diana; HENKEL, Jörk.IEEE transactions on very large scale integration (VLSI) systems. 2008, Vol 16, Num 6, pp 609-682, issn 1063-8210, 73 p.Conference Paper
A New Scan Power Reduction Scheme Using Transition Freezing for Pseudo-Random Logic BISTKIM, Youbean; KIM, Kicheol; KIM, Incheol et al.IEICE transactions on information and systems. 2008, Vol 91, Num 4, pp 1185-1188, issn 0916-8532, 4 p.Article
Performance of U02 ceramic fuel in low-power research reactorsALBARHOUM, M.Progress in nuclear energy (New series). 2011, Vol 53, Num 1, pp 73-75, issn 0149-1970, 3 p.Article
Low-Power Snoop Architecture for Synchronized Producer-Consumer Embedded MultiprocessingCHENJIE YU; PETROV, Peter.IEEE transactions on very large scale integration (VLSI) systems. 2009, Vol 17, Num 9, pp 1362-1366, issn 1063-8210, 5 p.Article
SoC issues for RF smart dustCOOK, Ben W; LANZISERA, Steven; PISTER, Kristofer S. J et al.Proceedings of the IEEE. 2006, Vol 94, Num 6, pp 1177-1196, issn 0018-9219, 20 p.Article
Noise metrics in flip-flop designsELGAMEL, Mohammed A; FAISAL, Md Ibrahim; BAYOUMI, Magdy A et al.IEICE transactions on information and systems. 2005, Vol 88, Num 7, pp 1501-1505, issn 0916-8532, 5 p.Article
Standby power reduction using dynamic voltage scaling and canary flip-flop structuresCALHOUN, Benton H; CHANDRAKASAN, Anantha P.IEEE journal of solid-state circuits. 2004, Vol 39, Num 9, pp 1504-1511, issn 0018-9200, 8 p.Article
Memory system optimization of embedded softwareWOLF, Wayne; KANDEMIR, Mahmut.Proceedings of the IEEE. 2003, Vol 91, Num 1, pp 165-182, issn 0018-9219, 18 p.Article
Low power block-based watermarking algorithmPAI, Yu-Ting; RUAN, Shang-Jang.IEICE transactions on information and systems. 2006, Vol 89, Num 4, pp 1507-1514, issn 0916-8532, 8 p.Article
Watch-dog circuit for quality guarantee with subthreshold MOSFET current : New system paradigms for integrated electronicsHIROSE, Tetsuya; YOSHIMURA, Ryuji; IDO, Toru et al.IEICE transactions on electronics. 2004, Vol 87, Num 11, pp 1910-1914, issn 0916-8524, 5 p.Article
A fragmentation aware High-Level Synthesis flow for low power heterogenous datapathsDEL BARRIO, Alberto A; OGRENCI MEMIK, Seda; MOLINA, María C et al.Integration (Amsterdam). 2013, Vol 46, Num 2, pp 119-130, issn 0167-9260, 12 p.Article
An energy-efficient partitioned instruction cache architecture for embedded processorsKIM, Cheolhong; CHUNG, Sungwoo; JHON, Chushik et al.IEICE transactions on information and systems. 2006, Vol 89, Num 4, pp 1450-1458, issn 0916-8532, 9 p.Article
Instruction buffering for nested loops in low-power designCHITA WU; HSIEH, Ang-Chih; TINGTING HWANG et al.IEEE transactions on very large scale integration (VLSI) systems. 2006, Vol 14, Num 7, pp 780-784, issn 1063-8210, 5 p.Article
Power and Area Optimization for Run-Time Reconfiguration System On Programmable Chip Based on Magnetic Random Access MemoryWEISHENG ZHAO; BELHAIRE, Eric; CHAPPERT, Claude et al.IEEE transactions on magnetics. 2009, Vol 45, Num 2, pp 776-780, issn 0018-9464, 5 p., 1Article
Simulation of a neural node using SET technologyVAN DE HAAR, Rudie; HOEKSTRA, Jaap.Lecture notes in computer science. 2003, pp 377-386, issn 0302-9743, isbn 3-540-00730-X, 10 p.Conference Paper
An advanced PNP bipolar transistor design for low-power and very-high-performance quarter-micron CBiCMOS processDJEZZAR, B; BELAROUSSI, M. T.International conference on microelectronic. 1997, pp 509-512, isbn 0-7803-3664-X, 2VolConference Paper