Pascal and Francis Bibliographic Databases

Help

Search results

Your search

kw.\*:("low-power design")

Publication Year[py]

A-Z Z-A Frequency ↓ Frequency ↑
Export in CSV

Discipline (document) [di]

A-Z Z-A Frequency ↓ Frequency ↑
Export in CSV

Author Country

A-Z Z-A Frequency ↓ Frequency ↑
Export in CSV

Results 1 to 25 of 107

  • Page / 5
Export

Selection :

  • and

Low Power Magnetic Full-Adder Based on Spin Transfer Torque MRAMERYA DENG; YUE ZHANG; KLEIN, Jacques-Olivier et al.IEEE transactions on magnetics. 2013, Vol 49, Num 9, pp 4982-4987, issn 0018-9464, 6 p.Article

An energy-efficient partitioned instruction cache architecture for embedded processorsKIM, Cheolhong; CHUNG, Sungwoo; JHON, Chushik et al.IEICE transactions on information and systems. 2006, Vol 89, Num 4, pp 1450-1458, issn 0916-8532, 9 p.Article

Instruction buffering for nested loops in low-power designCHITA WU; HSIEH, Ang-Chih; TINGTING HWANG et al.IEEE transactions on very large scale integration (VLSI) systems. 2006, Vol 14, Num 7, pp 780-784, issn 1063-8210, 5 p.Article

Fully Pipelined Bloom Filter ArchitecturePAYNTER, Michael; KOCAK, Taskin.IEEE communications letters. 2008, Vol 12, Num 11, pp 855-857, issn 1089-7798, 3 p.Article

Power-Aware High-Level Synthesis With Clock Skew ManagementYEH, Tung-Hua; WANG, Sying-Jyan.IEEE transactions on very large scale integration (VLSI) systems. 2012, Vol 20, Num 1, pp 167-171, issn 1063-8210, 5 p.Article

Gated Decap: Gate Leakage Control of On-Chip Decoupling Capacitors in Scaled TechnologiesYIRAN CHEN; HAI LI; ROY, Kaushik et al.IEEE transactions on very large scale integration (VLSI) systems. 2009, Vol 17, Num 12, pp 1749-1752, issn 1063-8210, 4 p.Article

Enhanced leakage reduction techniques using intermediate strength power gatingSINGH, Harmander; AGARWAL, Kanak; SYLVESTER, Dennis et al.IEEE transactions on very large scale integration (VLSI) systems. 2007, Vol 15, Num 11, pp 1215-1224, issn 1063-8210, 10 p.Article

Relative timingSTEVENS, Kenneth S; GINOSAR, Ran; ROTEM, Shai et al.IEEE transactions on very large scale integration (VLSI) systems. 2003, Vol 11, Num 1, pp 129-140, issn 1063-8210, 12 p.Article

A low-power reduced swing global clocking methodologyFARHAD HAJ ALI ASGARI; SACHDEV, Manoj.IEEE transactions on very large scale integration (VLSI) systems. 2004, Vol 12, Num 5, pp 538-545, issn 1063-8210, 8 p.Article

Robust and Energy Efficient Multimedia Systems via Likelihood Processing : NEW SOFTWARE/HARDWARE PARADIGMS FOR ERROR-TOLERANT MULTIMEDIA SYSTEMSABDALLAH, Rami A; SHANBHAG, Naresh R.IEEE transactions on multimedia. 2013, Vol 15, Num 2, pp 257-267, issn 1520-9210, 11 p.Article

A comparative study on gate leakage and performance of high-K nano-CMOS logic gatesKOUGIANOS, Elias; MOHANTY, Saraju P.International journal of electronics. 2010, Vol 97, Num 9-10, pp 985-1005, issn 0020-7217, 21 p.Article

Energy-Efficient Design Methodologies: High-Performance VLSI AddersZEYDEL, Bart R; BARAN, Dursun; OKLOBDZIJA, Vojin G et al.IEEE journal of solid-state circuits. 2010, Vol 45, Num 6, pp 1220-1233, issn 0018-9200, 14 p.Article

Low-power design of high-speed A/D converters : Lower-power LSI and lower-power IPKAWAHITO, Shoji; HONDA, Kazutaka; FURUTA, Masanori et al.IEICE transactions on electronics. 2005, Vol 88, Num 4, pp 468-478, issn 0916-8524, 11 p.Article

Static energy reduction techniques for microprocessor cachesHANSON, Heather; HRISHIKESH, M. S; AGARWAL, Vikas et al.IEEE transactions on very large scale integration (VLSI) systems. 2003, Vol 11, Num 3, pp 303-313, issn 1063-8210, 11 p.Conference Paper

Avalanche: An environment for design space exploration and optimization of low-power embedded systemsHENKEL, Jörg SR; YANBING LI.IEEE transactions on very large scale integration (VLSI) systems. 2002, Vol 10, Num 4, pp 454-468, issn 1063-8210, 15 p.Article

Battery-powered digital CMOS designPEDRAM, Massoud; QING WU.IEEE transactions on very large scale integration (VLSI) systems. 2002, Vol 10, Num 5, pp 601-607, issn 1063-8210, 7 p.Article

A Low-Power Fractional-Order Synchronizer for Syncless Time-Sequential Synchronization of 3-D TV Active Shutter GlassesPARK, Daejin; CHANG MIN KIM; KWAK, Sungho et al.IEEE transactions on circuits and systems for video technology. 2013, Vol 23, Num 2, pp 364-369, issn 1051-8215, 6 p.Article

Dynamic Bit-Width Adaptation in DCT: An Approach to Trade Off Image Quality and Computation EnergyPARK, Jongsun; JUNG HWAN CHOI; ROY, Kaushik et al.IEEE transactions on very large scale integration (VLSI) systems. 2010, Vol 18, Num 5, pp 787-793, issn 1063-8210, 7 p.Article

An Energy Efficient 40 Kb SRAM Module With Extended Read/Write Noise Margin in 0.13 μm CMOSSHARIFKHANI, Mohammad; SACHDEV, Manoj.IEEE journal of solid-state circuits. 2009, Vol 44, Num 2, pp 620-630, issn 0018-9200, 11 p.Article

Operation mode based high-level switching activity analysis for power estimation of digital circuitsSHIN, Hyunchul; LEE, Changhee.IEICE transactions on communications. 2007, Vol 90, Num 7, pp 1826-1834, issn 0916-8516, 9 p.Article

A CAM with mixed serial-parallel comparison for use in low energy cachesEFTHYMIOU, Aristides; GARSIDE, Jim D.IEEE transactions on very large scale integration (VLSI) systems. 2004, Vol 12, Num 3, pp 325-329, issn 1063-8210, 5 p.Article

An asynchronous ternary logic signaling systemFELICIJAN, Tomaz; FURBER, Steve B.IEEE transactions on very large scale integration (VLSI) systems. 2003, Vol 11, Num 6, pp 1114-1119, issn 1063-8210, 6 p.Article

Location Cache Design and Performance Analysis for Chip Multiprocessors : Performance-Noise AnalysisNEMETH, Jason; RUI MIN; JONE, Wen-Ben et al.IEEE transactions on very large scale integration (VLSI) systems. 2011, Vol 19, Num 1, pp 104-117, issn 1063-8210, 14 p.Article

A Methodology for the Design of MOS Current-Mode Logic CircuitsCARUSO, Giuseppe; MACCHIARELLA, Alessio.IEICE transactions on electronics. 2010, Vol 93, Num 2, pp 172-181, issn 0916-8524, 10 p.Article

An overview of the competitive and adversarial approaches to designing dynamic power management strategiesIRANI, Sandy; SINGH, Gaurav; SHUKLA, Sandeep K et al.IEEE transactions on very large scale integration (VLSI) systems. 2005, Vol 13, Num 12, pp 1349-1361, issn 1063-8210, 13 p.Article

  • Page / 5