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Results 1 to 25 of 874

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A Nitride-Based P-Channel Logic-Compatible One-Time-Programmable Cell With a New Contact Select GateTSAI, Yi-Hung; LIN, Kai-Chun; KUO, Cheng-Hsiung et al.IEEE electron device letters. 2009, Vol 30, Num 10, pp 1090-1092, issn 0741-3106, 3 p.Article

Asymmetric fingered polysilicon p-channel thin film transistor structure for kink effect suppressionBONFIGLIETTI, A; CUSCUNA, M; RAPISARDA, M et al.Thin solid films. 2007, Vol 515, Num 19, pp 7433-7436, issn 0040-6090, 4 p.Conference Paper

P-Channel MOSFETs on 4H-SiC {0001} and Nonbasal Faces Fabricated by Oxide Deposition and N20 AnnealingNOBORIO, Masato; SUDA, Jun; KIMOTO, Tsunenobu et al.I.E.E.E. transactions on electron devices. 2009, Vol 56, Num 9, pp 1953-1958, issn 0018-9383, 6 p.Article

Synthesis, physical properties, and field-effect transistors of novel thiophene/thiazolothiazole co-oligomersANDO, Shinji; NISHIDA, Jun-Ichi; INOUE, Youji et al.Journal of material chemistry. 2004, Vol 14, Num 12, pp 1787-1790, issn 0959-9428, 4 p.Article

Lateral extension engineering using nitrogen implantation (N-tub) for high-performance 40-nm pMOSFETsMOMIYAMA, Y; OKABE, K; NAKAO, H et al.IEDm : international electron devices meeting. 2002, pp 647-650, isbn 0-7803-7462-2, 4 p.Conference Paper

A sub-400°C germanium MOSFET technology with high-κ dielectric and metal gateCHI ON CHUI; KIM, Hyoungsub; CHI, David et al.IEDm : international electron devices meeting. 2002, pp 437-440, isbn 0-7803-7462-2, 4 p.Conference Paper

BSIM4.1 DC parameter extraction on 50 nm n-pMOSFETsSOUIL, D; GUEGAN, G; BERTRAND, G et al.2002 international conference on microelectronic test structures. 2002, pp 115-119, isbn 0-7803-7464-9, 5 p.Conference Paper

NBTI mechanism in ultra-thin gate dielectric: Nitrogen-originated mechanism in SiONMITANI, Yuichiro; NAGAMINE, Makoto; SATAKE, Hideki et al.IEDm : international electron devices meeting. 2002, pp 509-512, isbn 0-7803-7462-2, 4 p.Conference Paper

A predictive reliability model for PMOS bias temperature degradationMAHAPATRA, S; ALAM, M. A.IEDm : international electron devices meeting. 2002, pp 505-508, isbn 0-7803-7462-2, 4 p.Conference Paper

A new half-micrometer p-channel MOSFET with efficient punchthrough stopsODANAKA, S; FUKUMOTO, M; FUSE, G et al.I.E.E.E. transactions on electron devices. 1986, Vol 33, Num 3, pp 317-321, issn 0018-9383Article

High-Voltage PMOS Transistor Model for Prediction of Susceptibility to Conducted InterferenceJOVIC, Ognjen; MAIER, Christian; BARIC, Adrijan et al.IEEE transactions on electromagnetic compatibility. 2011, Vol 53, Num 1, pp 53-62, issn 0018-9375, 10 p.Article

Performance evaluation of field-enhanced p-channel split-gate flash memoryCHU, Wen-Ting; LIN, Hao-Hsiung; WANG, Yu-Hsiung et al.IEEE electron device letters. 2005, Vol 26, Num 9, pp 670-672, issn 0741-3106, 3 p.Article

Inspection of the Current-Mirror Mismatch by Secondary Electron Potential Contrast With In Situ Nanoprobe BiasingLIU, Po-Tsun; LEE, Jeng-Han.IEEE electron device letters. 2011, Vol 32, Num 10, pp 1418-1420, issn 0741-3106, 3 p.Article

Germanium―Tin (GeSn) p-Channel MOSFETs Fabricated on (100) and (111) Surface Orientations With Sub-400 °C Si2H6 PassivationXIAO GONG; GENQUAN HAN; BUWEN CHENG et al.IEEE electron device letters. 2013, Vol 34, Num 3, pp 339-341, issn 0741-3106, 3 p.Article

Layout-Dependent Strain Optimization for p-Channel Trigate TransistorsMUJUMDAR, Salil; MAITRA, Kingsuk; DATTA, Suman et al.I.E.E.E. transactions on electron devices. 2012, Vol 59, Num 1, pp 72-78, issn 0018-9383, 7 p.Article

Back gate influence on front channel operation of p-channel double gate polysilicon TFTsMICHALAS, L; PAPAIOANNOU, G. J; KOUVATSOS, D. N et al.Thin solid films. 2009, Vol 517, Num 23, pp 6364-6366, issn 0040-6090, 3 p.Conference Paper

Solid phase crystallisation using inline furnace systemKIM, M. J; JIN, G. H; YU, C. H et al.Electronics letters. 2011, Vol 47, Num 17, pp 978-980, issn 0013-5194, 3 p.Article

A physical model for the gate current injection in p-channel MOSFET'sIH-CHIN CHEN; WANG, S. J.IEEE electron device letters. 1993, Vol 14, Num 5, pp 228-230, issn 0741-3106Article

Short-channel pMOST's in a high-resistivity silicon substrate. II: Noise performanceVANSTRAELEN, G; SIMOEN, E; DECLERCK, G. J et al.I.E.E.E. transactions on electron devices. 1992, Vol 39, Num 10, pp 2278-2283, issn 0018-9383Article

A simple method for sub-100 nm pattern generation with I-line double-patterning techniqueTSAI, Tzu-I; LIN, Horng-Chih; JIAN, Min-Feng et al.Microelectronics and reliability. 2010, Vol 50, Num 5, pp 584-588, issn 0026-2714, 5 p.Article

CMOS scaling for sub-90 nm to sub-10 nmIWAI, Hiroshi.International Conference on Embedded Systems DesignInternational Conference on VLSI Design. 2004, pp 30-35, isbn 0-7695-2072-3, 1Vol, 6 p.Conference Paper

High-performance single-crystalline-silicon TFTs on a non-alkali glass substrateSANO, Yasuyuki; TAKEI, Michiko; HARA, Akito et al.IEDm : international electron devices meeting. 2002, pp 565-568, isbn 0-7803-7462-2, 4 p.Conference Paper

Characteristics and device design of sub-100 nm strained si N- and PMOSFETsRIM, K; CHU, J; OTT, J et al.Symposium on VLSI technology. 2002, pp 98-99, isbn 0-7803-7312-X, 2 p.Conference Paper

Transistors with dual work function metal gates by single full silicidation (FUSI) of polysilicon gatesMASZARA, W. P; KRIVOKAPIC, Z; KING, P et al.IEDm : international electron devices meeting. 2002, pp 367-370, isbn 0-7803-7462-2, 4 p.Conference Paper

Monte Carlo simulation of PHEMTs operating up to terahertz frequenciesHOARE, D; ABRAM, R. A.International journal of electronics. 1997, Vol 83, Num 4, pp 429-439, issn 0020-7217Article

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