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Data retention of silicon nanocrystal storage nodes programmed with short voltage pulsesPUZZILLI, Giuseppina; IRRERA, Fernanda.I.E.E.E. transactions on electron devices. 2006, Vol 53, Num 4, pp 775-781, issn 0018-9383, 7 p.Article

Poly-Si Thin-Film Transistor Nonvolatile Memory Using Ge Nanocrystals as a Charge Trapping Layer Deposited by the Low-Pressure Chemical Vapor DepositionKUO, Po-Yi; CHAO, Tien-Sheng; HUANG, Jyun-Siang et al.IEEE electron device letters. 2009, Vol 30, Num 3, pp 234-236, issn 0741-3106, 3 p.Article

Physical Modeling for Programming of TANOS Memories in the Fowler-Nordheim RegimeMONZIO COMPAGNONI, Christian; MAURI, Aurelio; AMOROSO, Salvatore Maria et al.I.E.E.E. transactions on electron devices. 2009, Vol 56, Num 9, pp 2008-2015, issn 0018-9383, 8 p.Article

The 1/f Noise and Random Telegraph Noise Characteristics in Floating-Gate NAND Flash MemoriesBAE, Sung-Ho; LEE, Jeong-Hyun; KWON, Hyuck-In et al.I.E.E.E. transactions on electron devices. 2009, Vol 56, Num 8, pp 1624-1630, issn 0018-9383, 7 p.Article

Reduced Multilayer Graphene Oxide Floating Gate Flash Memory With Large Memory Window and Robust Retention CharacteristicsMISHRA, Abhishek; JANARDANAN, Amritha; KHARE, Manali et al.IEEE electron device letters. 2013, Vol 34, Num 9, pp 1136-1138, issn 0741-3106, 3 p.Article

Impact of SiN Composition Variation on SANOS Memory Performance and Reliability Under NAND (FN/FN) OperationSANDHYA, C; OAK, Apoorva B; MAHAPATRA, Souvik et al.I.E.E.E. transactions on electron devices. 2009, Vol 56, Num 12, pp 3123-3132, issn 0018-9383, 10 p.Article

Threshold-Voltage Instability Due to Damage Recovery in Nanoscale NAND Flash MemoriesMICCOLI, Carmine; MONZIO COMPAGNONI, Christian; BELTRAMI, Silvia et al.I.E.E.E. transactions on electron devices. 2011, Vol 58, Num 8, pp 2406-2414, issn 0018-9383, 9 p.Article

An overview of logic architectures inside Flash memory devicesSILVAGNI, Andrea; FUSILLO, Giuseppe; RAVASIO, Roberto et al.Proceedings of the IEEE. 2003, Vol 91, Num 4, pp 569-580, issn 0018-9219, 12 p.Article

Electrical Characteristics for Flash Memory With Germanium Nitride as the Charge-Trapping LayerLIN, Chia-Chun; WU, Yung-Hsien; LIN, Yuan-Sheng et al.IEEE transactions on nanotechnology. 2013, Vol 12, Num 3, pp 436-441, issn 1536-125X, 6 p.Article

Comparative Analysis of Bandgap-Engineered Pillar Type Flash Memory with HfO2 and S3N4 as Trapping Layer : Fundamentals and Applications of Advanced Semiconductor DevicesLEE, Sang-Youl; YANG, Seung-Dong; OH, Jae-Sub et al.IEICE transactions on electronics. 2012, Vol 95, Num 5, pp 831-836, issn 0916-8524, 6 p.Article

Electrical characteristics of memory devices with a High-k HfO2 trapping layer and dual SiO2 /Si3N4 tunneling layerYING QIAN WANG; WAN SIK HWANG; GANG ZHANG et al.I.E.E.E. transactions on electron devices. 2007, Vol 54, Num 10, pp 2699-2705, issn 0018-9383, 7 p.Article

Designed Workfunction Engineering of Double-Stacked Metal Nanocrystals for Nonvolatile Memory ApplicationRYU, Seong-Wan; LEE, Jong-Won; HAN, Jin-Woo et al.I.E.E.E. transactions on electron devices. 2009, Vol 56, Num 3, pp 377-382, issn 0018-9383, 6 p.Article

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