Novel process for emitter-base-collector self-aligned heterojunction bipolar transistor using a pattern-inversion methodTANAKA, S; MADIHIAN, M; TOYOSHIMA, H et al.Electronics Letters. 1987, Vol 23, Num 11, pp 562-564, issn 0013-5194Article

High yield reduced process tolerance self-aligned double mesa process technology for SiGe power HBTsLEE, Kok-Yan; JOHNSON, Brian N; MOHAMMADI, Saeed et al.IEEE MTT-S International Microwave Symposium. 2004, isbn 0-7803-8331-1, vol2, 963-966Conference Paper

A self-aligned double-gate MOS transistor technology with individually addressable gatesZHANG, Shengdong; LIN, Xinnan; HUANG, Ru et al.IEEE International SOI conference. 2002, pp 207-208, isbn 0-7803-7439-8, 2 p.Conference Paper

Reliability characterization of high-speed CMOS logic ICsGOTTESFELD, S; GIBBONS, L.RCA review. 1984, Vol 45, Num 2, pp 179-193, issn 0033-6831Article

Fin width scaling criteria of body-tied FinFET in sub-50 nm regimeHYE JIN CHO; JEONG DONG CHOE; MING LI et al.DRC : Device research conference. 2004, pp 209-210, isbn 0-7803-8284-6, 1Vol, 2 p.Conference Paper

Bulk inversion in FinFETs and the implied insignificance of the effective gate widthKIM, S.-H; FOSSUM, J. G; TRIVEDI, V. P et al.IEEE international SOI conference. 2004, pp 145-147, isbn 0-7803-8497-0, 1Vol, 3 p.Conference Paper

Emitter-base-collector self-aligned heterojunction bipolar transistors using wet etching processEDA, K; INADA, M; OTA, Y et al.IEEE electron device letters. 1986, Vol 7, Num 12, pp 694-696, issn 0741-3106Article

A survey of sequence alignment algorithms for next-generation sequencingHENG LI; HOMER, Nils.Briefings in bioinformatics. 2010, Vol 11, Num 5, pp 473-483, issn 1467-5463, 11 p.Article

Two-dimensional effects in the bipolar polysilicon self-aligned transistorVERRET, D. P; BRIGHTON, J. E.I.E.E.E. transactions on electron devices. 1987, Vol 34, Num 11, pp 2297-2303, issn 0018-9383Article

Identification and implication of a perimeter tunneling current component in advanced self-aligned bipolar transistorsLI, G. P; HACKBARTH, E; TZE-CHIANG CHEN et al.I.E.E.E. transactions on electron devices. 1988, Vol 35, Num 1, pp 89-95, issn 0018-9383Article

A new polysilicon CMOS self-aligned double-gate TFT technologyZHIBIN XIONG; HAITAO LIU; CHUNXIANG ZHU et al.I.E.E.E. transactions on electron devices. 2005, Vol 52, Num 12, pp 2629-2633, issn 0018-9383, 5 p.Article

TECHNOLOGY OF A NEW N-CHANNEL ONE-TRANSISTOR EAROM CELL CALLED SIMOS.SCHEIBE A; SCHULTE H.1977; I.E.E.E. TRANS-ELECTRON DEVICES; U.S.A.; DA. 1977; VOL. 24; NO 5; PP. 600-606; BIBL. 7 REF.Article

Compressor technologies for low temperature applications of R-22DIAB, T. A. R; GEPHART, J.International journal of refrigeration. 1991, Vol 14, Num 1, pp 5-9, issn 0140-7007, 5 p.Article

New meaning to IT alignment : Aligning it with the business strategyMOODY, Kavin W.Information systems management. 2003, Vol 20, Num 4, pp 30-35, issn 1058-0530, 6 p.Article

Integrated-circuit test structure which uses a vernier to electrically measure mask misalignmentHENDERSON, B. M. M; GUNDLACH, A. M; WALTON, A. J et al.Electronics Letters. 1983, Vol 19, Num 21, pp 868-869, issn 0013-5194Article

On the Scaling of Flash Cell Spacer for Gate Disturb and Charge Retention OptimizationLEE, Yung-Huei; MCMAHON, William; LU, Yin-Lung Ryan et al.I.E.E.E. transactions on electron devices. 2009, Vol 56, Num 9, pp 1959-1965, issn 0018-9383, 7 p.Article

DEVICE TECHNOLOGY. ADVANCED DEVICE AND PROCESSING CONCEPTS1979; IEDM 1979. INTERNATIONAL ELECTRON DEVICES MEETING/1979/WASHINGTON DC; USA; NEW YORK: IEEE; DA. 1979; PP. 575-604; BIBL. DISSEM.Conference Paper

The Important Challenge to Extend Spacer DP process towards 22nm and beyondOYAMA, Kenichi; NISIMURA, Eiichi; YAMAJI, Tomohito et al.Proceedings of SPIE, the International Society for Optical Engineering. 2010, Vol 7639, issn 0277-786X, isbn 978-0-8194-8053-8 0-8194-8053-3, 763907.1-763907.6, 2Conference Paper

Improved self-aligned structure for GaAlAs high-power lasersYOSHIZAWA, M; UOMI, K; OHISHI, A et al.Japanese journal of applied physics. 1987, Vol 26, Num 9, pp L1465-L1467, issn 0021-4922, 2Article

A sub-400°C germanium MOSFET technology with high-κ dielectric and metal gateCHI ON CHUI; KIM, Hyoungsub; CHI, David et al.IEDm : international electron devices meeting. 2002, pp 437-440, isbn 0-7803-7462-2, 4 p.Conference Paper

AlGaAs/GaAs heterojunction bipolar transistors fabricated using a self-aligned dual-lift-off processCHANG, M.-C. F; ASBECK, P. M; WANG, K. C et al.IEEE electron device letters. 1987, Vol 8, Num 7, pp 303-305, issn 0741-3106Article

Silicon oxide enhanced Schottky gate In_0.53Ga_0.47AsFET's with a self-aligned recessed gate structureCHENG, C. L; LIAO, A. S. H; CHANG, T. Y et al.IEEE electron device letters. 1984, Vol 5, Num 12, pp 511-514, issn 0741-3106Article

A SIMPLIFIED SELF-ALIGNED AL-GATE MOS TECHNOLOGY FOR HIGH PERFORMANCE DEPLETION-LOGIC CIRCUITSPEREIRA DE SOUZA J; CHARRY E.1979; I.E.E.E. J. SOLID-STATE CIRCUITS; USA; DA. 1979; VOL. 14; NO 3; PP. 651-653; BIBL. 7 REF.Article

Fully-depleted FBC (Floating Body Cell) with enlarged signal window and excellent logic process compatibilitySHINO, Tomoaki; HIGASHI, Tomoki; NAKAJIMA, Hiroomi et al.International Electron Devices Meeting. 2004, pp 281-284, isbn 0-7803-8684-1, 1Vol, 4 p.Conference Paper

Design of experiment on the CO salicide process: Impact of thickness and anneals on main CMOS parametersWACQUANT, F; REGNIER, C; BASSO, M.-T et al.Proceedings - Electrochemical Society. 2003, pp 191-196, issn 0161-6374, isbn 1-56677-396-2, 6 p.Conference Paper